Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 415 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 12-17
Two Wire Interface Controller
This interrupt has occurred due to the completion of the data
receive transfer. If no errors were generated, a start condition is ini-
tiated. Clear the
RSTART
bit and program the
DCNT
with the desired
number of bytes to transmit.
•
XMTSERV
interrupt
This interrupt is generated due to a FIFO access. Simple data han-
dling is all that is required.
•
MCOMP
interrupt
The transfer is complete.

There is no timing constraint to meet the above conditions—the
user can program the bits as required. Refer to
“Clock Stretching
During Repeated Start Condition” on page 12-20 for more on how
the controller stretches the clock during Repeated Start transfers.
Clock Stretching
Clock stretching is an added functionality of the TWI controller in Master
Mode operation. This new behavior utilizes self-induced stretching of the
I
2
C clock while waiting on servicing interrupts. Stretching is done auto-
matically by the hardware and no programming is required for this.
The TWI Controller as Master supports three modes of clock stretching:
“Clock Stretching During FIFO Underflow” on page 12-17 , “Clock
Stretching During FIFO Overflow” on page 12-19 and “Clock Stretching
During Repeated Start Condition” on page 12-20 .
Clock Stretching During FIFO Underflow
During a master mode transmit, an interrupt is generated at the instant
the transmit FIFO becomes empty. At this time, the most recent byte
begins transmission. If the XMTSERV interrupt is not serviced, the con-
cluding “acknowledge” phase of the transfer will be stretched. Stretching