Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 150 / 772

Programming Model
5-50 ADSP-BF59x Blackfin Processor Hardware Reference
Programming Model
Several synchronization and control methods are available for use in devel-
opment of software tasks which manage peripheral DMA and memory
DMA (see also
“Memory DMA” on page 5-6 ). Such software needs to be
able to accept requests for new DMA transfers from other software tasks,
integrate these transfers into existing transfer queues, and reliably notify
other tasks when the transfers are complete.
In the processor, it is possible for each peripheral DMA and memory
DMA stream to be managed by a separate task or to be managed together
with any other stream. Each DMA channel has independent, orthogonal
control registers, resources, and interrupts, so that the selection of the
control scheme for one channel does not affect the choice of control
scheme on other channels. For example, one peripheral can use a
linked-descriptor-list, interrupt-driven scheme while another peripheral
can simultaneously use a demand-driven, buffer-at-a-time scheme syn-
chronized by polling of the
DMAx_IRQ_STATUS
register.
Synchronization of Software and DMA
A critical element of software DMA management is synchronization of
DMA buffer completion with the software. This can best be done using
interrupts, polling of
DMAx_IRQ_STATUS
, or a combination of both. Polling
for address or count can only provide synchronization within loose toler-
ances comparable to pipeline lengths.
Interrupt-based synchronization methods must avoid interrupt overrun,
or the failure to invoke a DMA channel’s interrupt handler for every inter-
rupt event due to excessive latency in processing of interrupts. Generally,
the system design must either ensure that only one interrupt per channel is
scheduled (for example, at the end of a descriptor list), or that interrupts
are spaced sufficiently far apart in time that system processing budgets can
guarantee every interrupt is serviced. Note, since every interrupt channel