Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 474 / 772

Functional Description
13-20 ADSP-BF59x Blackfin Processor Hardware Reference
These steps illustrate SPI operation in the slave mode:
1. The core writes to the appropriate port register(s) to properly con-
figure the SPI for slave mode operation.
2. The core writes to
SPI_CTL
to define the mode of the serial link to
be the same as the mode set up in the SPI master.
3. To prepare for the data transfer, the core writes data to be trans-
mitted into
SPI_TDBR
.
4. Once the
SPISS
falling edge is detected, the slave starts shifting
data out on
MISO
and in from
MOSI
on
SCK
edges, depending upon
the states of
CPHA
and
CPOL
.
5. Reception/transmission continues until
SPISS
is released or until
the slave has received the proper number of clock cycles.
6. The slave device continues to receive/transmit with each new fall-
ing edge transition on
SPISS
and/or
SCK
clock edge.
See Figure 13-8 on page 13-29 for additional information.
If the transmit buffer remains empty or the receive buffer remains full, the
device operates according to the states of the
SZ
and
GM
bits in
SPI_CTL
. If
SZ
= 1 and the transmit buffer is empty, the device repeatedly transmits
zeros on the
MISO
pin. If
SZ
= 0 and the transmit buffer is empty, it repeat-
edly transmits the last word it transmitted before the transmit buffer
became empty. If
GM
= 1 and the receive buffer is full, the device continues
to receive new data from the
MOSI
pin, overwriting the older data in the
SPI_RDBR
register. If
GM
= 0 and the receive buffer is full, the incoming
data is discarded, and the
SPI_RDBR
register is not updated.