Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 139 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 5-39
Direct Memory Access
the FIFO in its own
HMDMAx_ECOUNT
register. Theoretically, the MDMA
could immediately process data as soon as it is written into the FIFO by
the write strobe, but the fast MDMA engine would read out the FIFO
quickly and stall soon if the FIFO was not promptly filled with new data .
Streaming applications can balance the FIFO so that the producer is never
held off by a full FIFO and the consumer is never held by an empty FIFO.
This is accomplished by filling the FIFO halfway and then letting both
consumer and producer run at the same speed. In this case the
HMDMAx_ECINIT
register can be written with a negative value, which corre-
sponds to half the FIFO depth. Then, the MDMA does not start
consuming data as long as the FIFO is not half-filled.
On internal system buses, memory DMA channels have lower priority
than other DMAs. In busy systems, the memory DMAs may tend to
starve. As this is not acceptable when transferring data through high-speed
FIFOs, the handshake mode provides a high-water functionality to
increase the MDMA’s priority. With the
UTE
bit in the
HMDMAx_CONTROL
register set, the MDMA gets higher priority as soon as a (positive) value in
the
HMDMAx_ECOUNT
register becomes higher than the threshold held by the
HMDMAx_ECURGENT
register.
HMDMA Interrupts
In addition to the normal MDMA interrupt channels, the handshake
hardware provides two new interrupt sources for each
DMARx
input. The
Figure 5-4. Receive DMA Example Connection
WR
AMSx
1024K x 16 FIFO BLACKFIN
FF
D0 .. D15
DMARx
RD
I0 .. I15 O0 .. O15
AWE