ADSP-BF59x Blackfin Processor Hardware Reference
9-7
Core Timer
Core Timer Scale Register (TSCALE)
The
TSCALE
register is shown in
Figure 9-5
. The register stores the scaling
value that is one less than the number of cycles between decrements of
TCOUNT
. For example, if the value in the
TSCALE
register is 0, the counter
register decrements once every
CCLK
clock cycle. If
TSCALE
is 1, the counter
decrements once every two cycles.
Programming Examples
Listing 9-1
configures the core timer in auto-reload mode. Assuming a
CCLK
of 500 MHz, the resulting period is 1 second. The initial period is
twice as long as the others.
Listing 9-1. Core Timer Configuration
#include <defBF527.h>/*ADSP-BF527 product is used as an example*/
.section L1_code;
.global _main;
_main:
/* Register service routine at EVT6 and unmask interrupt */
p1.l = lo(IMASK);
p1.h = hi(IMASK);
Figure 9-5. Core Timer Scale Register
31 30
29 28
27 26
25 24
23 22
21 20
19
18 17 16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
15 14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Core Timer
S
cale Register (T
S
CALE)
Reset = Undefined
S
cale Value[7:0]
Summary of Contents for ADSP-BF59x Blackfin
Page 64: ...Development Tools 1 22 ADSP BF59x Blackfin Processor Hardware Reference...
Page 74: ...Processor Specific MMRs 2 10 ADSP BF59x Blackfin Processor Hardware Reference...
Page 244: ...Programming Examples 6 40 ADSP BF59x Blackfin Processor Hardware Reference...
Page 700: ...Programming Examples 16 78 ADSP BF59x Blackfin Processor Hardware Reference...
Page 738: ...Boundary Scan Architecture B 8 ADSP BF59x Blackfin Processor Hardware Reference...