Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 340 / 772

Core Timer Registers
9-4 ADSP-BF59x Blackfin Processor Hardware Reference
controller (SIC). Therefore, the interrupt processing is also completely in
the
CCLK
domain.

The core timer interrupt request is edge-sensitive and cleared by
hardware automatically as soon as the interrupt is serviced.
The
TINT
bit in the
TCNTL
register indicates that an interrupt has been gen-
erated. Note that this is not a W1C bit. Write a 0 to clear it. However, the
write is optional. It is not required to clear interrupt requests. The core
time module doesn’t provide any further interrupt enable bit. When the
timer is enabled, interrupts can be masked in the CEC controller.
Core Timer Registers
The core timer includes four core memory-mapped registers, the timer
control register (
TCNTL
), the timer count register (
TCOUNT
), the timer
period register (
TPERIOD
), and the timer scale register (
TSCALE
). As with all
core MMRs, these registers are always accessed by 32-bit read and write
operations.