Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 757 / 772

ADSP-BF59x Blackfin Processor Hardware Reference I-19
Index
peripheral map registers
(DMAx_PERIPHERAL_MAP), 5-66
(MDMA_yy_PERIPHERAL_MAP),
5-66
peripheral pins, default configuration, 7-7
peripherals, 1-3
and buses, 1-3
compatible with SPI, 13-3
and DMA controller, 5-31
DMA support, 1-4
enabling, 7-2
interrupt generated by, 4-8
interrupts, clearing, 4-13
level-sensitivity of interrupts, 4-15
list of, 1-3
mapping to DMA, 5-103
multiplexing, 7-1
remapping DMA assignment, 5-6
switching from DMA to non-DMA,
5-73
timing, 3-3
used to wake from idle, 4-6
PF0 pin, 7-10
PFx pin, 13-7
phase locked loop, See PLL
pin information,
17-1
pins, 17-1
GPIO, 7-7
multiplexing, 7-1
unused, 17-8
pin terminations, SPORT, 14-8
pipeline, lengths of, 5-51
pipelining
DMA requests, 5-37
PLL, 6-1 to 6-28
active (enabled but bypassed) mode, 6-8
active mode, 6-8
applying power to the PLL, 6-11
block diagram, 6-3
BYPASS bit, 6-9
PLL (continued)
CCLK derivation, 6-3
changing clock ratio, 6-6
clock control, 6-1
clock dividers, 6-4
clock multiplier ratios, 6-3
configuration, 6-3
control bits, 6-10
deep sleep mode, 6-9
design overview, 6-2
disabled, 6-11
divide frequency, 6-4
DMA access, 6-8 , 6-9
dynamic power management controller
(DPMC), 6-7
enabled, 6-11
hibernate state, 6-10
interacting with DPMC, 6-2
and internal clocks, 3-3
maximum performance mode, 6-8
modification in active mode, 6-11
multiplier select (MSEL) field, 6-4
operating modes, operational
characteristics, 6-7
operating mode transitions, 6-10 , 6-13
PDWN bit, 6-10
PLL_OFF bit, 6-11
PLL status (table), 6-7
power domains, 6-15
power savings by operating mode (table),
6-7
registers, table, 6-19
removing power to the PLL, 6-11
SCLK derivation, 6-2 , 6-3
sleep mode, 6-9
STOPCK bit, 6-10
voltage control, 6-7
PLL control (PLL_CTL) register, 6-3 , 6-4 ,
6-19 , 6-20