Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 48 / 772

DMA Support
1-6 ADSP-BF59x Blackfin Processor Hardware Reference
into two smaller blocks: one contains the control MMRs for all core func-
tions and the other contains the registers needed for setup and control of
the on-chip peripherals outside of the core. The MMRs are accessible only
in supervisor mode. They appear as reserved space to on-chip peripherals.
DMA Support
The processor has a DMA controller which supports automated data
transfers with minimal overhead for the core. DMA transfers can occur
between the internal memories and any of its DMA-capable peripherals.
DMA-capable peripherals include the SPORTs, SPI ports, UART, and
PPI. Each individual DMA-capable peripheral has at least one dedicated
DMA channel.
The DMA controller supports both one-dimensional (1D) and
two-dimensional (2-D) DMA transfers. DMA transfer initialization can
be implemented from registers or from sets of parameters called descriptor
blocks.
The 2-D DMA capability supports arbitrary row and column sizes up to
64K elements by 64K elements, and arbitrary row and column step sizes
up to +/- 32K elements. Furthermore, the column step size can be less
than the row step size, allowing implementation of interleaved data-
streams. This feature is especially useful in video applications where data
can be de-interleaved on the fly.
Examples of DMA types supported include:
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each full or
fractionally full buffer