Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 551 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 14-45
SPORT Controller
Register Writes and Effective Latency
When the SPORT is disabled (
TSPEN
and
RSPEN
cleared), SPORT register
writes are internally completed at the end of the
SCLK
cycle in which they
occurred, and the register reads back the newly-written value on the next
cycle.
When the SPORT is enabled to transmit (
TSPEN
set) or receive (
RSPEN
set),
corresponding SPORT configuration register writes are disabled (except
for
SPORT_RCLKDIV
,
SPORT_TCLKDIV
, and multichannel mode channel select
registers). The
SPORT_TX
register writes are always enabled;
SPORT_RX
,
SPORT_CHNL
, and
SPORT_STAT
are read-only registers.
After a write to a SPORT register, while the SPORT is disabled, any
changes to the control and mode bits generally take effect when the
SPORT is re-enabled.

Most configuration registers can only be changed while the
SPORT is disabled (
TSPEN
/
RSPEN
= 0). Changes take effect after the
SPORT is re-enabled. The only exceptions to this rule are the
TCLKDIV
/
RCLKDIV
registers and multichannel select registers.
SPORT_MCM2 Secondary multichannel
mode configuration register Configure this register before
enabling the SPORT
SPORT_MRCSn Receive channel selection registers Select or deselect channels in a mul-
tichannel frame
SPORT_MTCSn Transmit channel selection registers Select or deselect channels in a mul-
tichannel frame
SPORT_CHNL Currently serviced channel
in a multichannel frame
Table 14-5. SPORT Register Mapping (Continued)
Register Name Function Notes