Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 567 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 14-61
SPORT Controller
When the SPORT RX hold register is full, and a new receive word is
received in the shift register, the receive overflow status bit (
ROVF
) is set in
the
SPORT_STAT
register. It is a sticky W1C bit and is also cleared by dis-
abling the SPORT (writing
RXEN
= 0).
The
RUVF
bit is set when a read is attempted from the RX FIFO and it is
empty. It is a sticky W1C bit and is also cleared by writing
RXEN
= 0. The
RUVF
bit is updated even when the SPORT is disabled.
SPORT Transmit and Receive Serial Clock Divider
(SPORT_TCLKDIV and SPORT_RCLKDIV) Registers
The frequency of an internally generated clock is a function of the system
clock frequency (as seen at the
SCLK
pin) and the value of the 16-bit serial
clock divide modulus registers (the
SPORT_TCLKDIV
register, shown in
Figure 14-34 , and the
SPORT_RCLKDIV
register, shown in Figure 14-35 on
page 14-62 ).
Figure 14-33. SPORT Status Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
S PORT S tatus Register ( S PORT_ S TAT)
0 - Disabled
1 - Enabled
RUVF ( S ticky Receive Under-
flow S tatus) - W1C
RXNE (Receive FIFO Not
Empty
S tatus)
ROVF ( S ticky Receive Over-
flow S tatus) - W1C
TUVF ( S ticky Transmit Underflow S tatus) - W1C
0 - Disabled
1 - Enabled
0 - Empty
1 - Data present in FIFO
Reset = 0x0040
0 - Disabled
1 - Enabled
TOVF ( S ticky Transmit Overflow S tatus) - W1C
0 - Disabled
1 - Enabled
TXF (Transmit FIFO Full S tatus)
0 - Not full
1 - Full
TXHRE (Transmit Hold Register Empty)
0 - Not empty
1 - Empty