LSM 710 and LSM 780
ANNEX
Systems
Specifications of Trigger-Interface
Carl Zeiss
02/2010 M60-1-0025
e
23
Timing of the synchronization signals Stack out, Line out and Frame out
These signals are directly generated by the hardware and cannot be influenced by the software. They are
also not seen by the user software and cannot be used to generate any markers within the image
acquistion. They are highly precise tools to control external hardware. The signals are precise to the pixel
and depending on the chosen pixel time the time between the signal and the start of the image
acquistion varies.
The Line out signal is set 44 pixels before the first image pixel of each line.
The Frame out signal is set 42 pixels before the first image pixel of each frame.
The Stack out signal is set 40 pixels before the first image pixel of each Z-stack.
The signal itself is identical to the signal of the pixelclock but is only set for one pixel.
The Grabbing signal is set to high-level with the start of data grabbing and set to low-level with the stop
of data grabbing for each line.
Type/Voltage Range:
−
TTL signal level 3.3 V, CMOS low power consumption
−
5.0 V tolerant input/output for interfacing with 5 V logic
Load:
Output:
< 50 mA (internal serial 68 ohm resistor)
Input:
4.7 kOhm input impedance (internal 4.7 kOhm pullup to 3.3 V)
Trigger pulse description:
Signal output:
−
Low level < 0.4 V, high level > 2.4 V (I = 10 mA)
−
Slew rate 10 ns/V
−
Reaction time trigger out 8 msec typical
Signal input:
−
Low level <0.5 … 0.8 V, high level >2.0 … 5.5 V
−
Falling edge force interrupt
−
Pulse width to detect signal > 50 ns
−
Reaction time trigger in 16 msec typical
Caution:
−
Never apply more than 5 V or negative voltages to avoid any damage.
−
In and outputs are not galvanically decoupled.
−
Therefore proper measures for galvanic decoupling of external devices have to be taken (opto-
coupler etc.).
