Siemens SIMATIC ET 200AL, System Manual

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Digital I/O module F-DI 4+F-DQ 2x24VDC/2A, 4xM12 (6ES7146-5FF00-0BA0)
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Equipment Manual, V1.0, 05/2021, A5E51082342-AA
Switching of loads
C
C.1 Connecting capacitive loads
If an F-DI 4/F-DQ 2 Fail-Safe module is interconnected with loads that require little current
and have capacitance, this can lead to detection of a short circuit or overload. Reason: The
capacitance cannot be sufficiently discharged or charged during the configured readback
time of the bit pattern test.
Load capacitance can delay the voltage response as seen at the P- and M-switches of the
F-DI 4/F-DQ 2 Fail-Safe module digital outputs. For a capacitive load with capacitance C across
P and M, and a parallel load resistance R, the "Maximum readback time" needs to be in the
range of 2.0 to 2.5 time constant (R * C) of the load. This allows enough time for an
appreciable voltage change to be seen when you briefly de-energize an energized load during
bit pattern testing. If the resulting "Maximum readback time" is too long for your application,
you can reduce this time constant by adding parallel resistance across the load to reduce the
realized R * C time constant.
Alternatively, you can add a diode between the P-output and the load (capacitor and
resistors) so that when you turn off the output, the voltage on the capacitor is not present at
the P-output. Typically, power supplies with input capacitors that have reverse voltage
protection have this diode built into the power supply. Using the added diode, you can
greatly reduce the "Maximum readback time" to some portion of the hold-up time of the
power supply/capacitor. This reduced "Maximum readback time" allows the load to operate
normally (load stays ON) during the bit pattern tests.
Stray capacitance between the load circuit and ground, M, and P increases the time required
for the "Maximum readback time switch on test". When module diagnostics switch "ON" a P-
or M-switch to a de-energized load during bit pattern testing, both sides of the load are
driven towards L+ or M, limited by stray capacitance. This effect is typically small.
Your "Maximum readback time switch on test" setting should be long enough for the load
circuit voltage to react, but short enough that if one side of the load faults to P or M, testing
of the opposite switch should not cause the load to mechanically react.
Capacitive loads (including power supplies with input capacitors) with low series resistance
can have a large inrush current. If you have a large capacitive load, you should add series
resistance to reduce the inrush current to reduce the risk of opened fuses or overcurrent fault
detection on normal load switch ON events.