GD32F20x User Manual
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The IRC40K can be trimmed by TIMER4_CH3, user can get the clocks frequency, and adjust
the RTC and FWDGT counter. Please refer to TIMER4CH3_IREMAP in AFIO_PCF0 register.
System clock (CK_SYS) selection
After the system reset, the default CK_SYS source will be IRC8M and can be switched to
HXTAL or CK_PLL by changing the system clock switch bits, SCS, in the Clock configuration
register 0(RCU_CFG0). When the SCS value is changed, the CK_SYS will continue to
operate using the original clock source until the target clock source is stable. When a clock
source is directly or indirectly (by PLL) used as the CK_SYS, it is not possible to stop it.
HXTAL clock monitor (CKM)
The HXTAL clock monitor function is enabled by the HXTAL clock monitor enable bit, CKMEN,
in the control register (RCU_CTL). This function should be enabled after the HXTAL start-up
delay is completed and disabled after the HXTAL is stopped. Once the HXTAL failure is
detected, the HXTAL will be automatically disabled. The HXTAL clock stuck interrupt flag,
CKMIF, in the Interrupt register, RCU_INT, will be set and the HXTAL failure event will be
generated. This failure interrupt is connected to the Non-Maskable Interrupt, NMI, of the
Cortex-M3. If the HXTAL is selected as the clock source of CK_SYS, PLL and CK_RTC, the
HXTAL failure will force the CK_SYS source to IRC8M, the PLL will be disabled automatically.
If the HXTAL is selected as the clock source of PLL, the HXTAL failure will force the PLL
closed automatically.
Clock output capability
The clock output capability is ranging from 30 KHz to 60 MHz.
CK_OUT0
There are several clock signals can be selected via the CK_OUT0 clock source selection bits,
CKOUT0SEL, in the clock configuration register 0 (RCU_CFG0). The corresponding GPIO
pin should be configured in the properly Alternate Function I/O (AFIO) mode to output the
selected clock signal.
Table 5-1. Clock Output 0 source select
CKOUT0SEL
Clock Source
00xx
No Clock
0100
CK_SYS
0101
CK_IRC8M
0110
CK_HXTAL
0111
CK_PLL/2
1000
CK_PLL1
1001
(CK_PLL2)/2
1010
EXT1
1011
CK_PLL2
The CKOUT0 frequency can be reduced by a configurable binary divider, controlled by the
CKOUT0DIV[5:0] bits , in the configuration register 2, RCU_CFG2.
Summary of Contents for GD32F20 Series
Page 191: ...GD32F20x User Manual 191 Bits Fields Descriptions 31 0 TRNDATA 31 0 32 Bit Random data ...
Page 290: ...GD32F20x User Manual 290 conversion is ongoing ...
Page 325: ...GD32F20x User Manual 325 15 0 ALRM 15 0 RTC alarm value low ...
Page 385: ...GD32F20x User Manual 385 ...
Page 523: ...GD32F20x User Manual 523 clears AERR bit by writing 0 to it ...