GigaDevice Semiconductor GD32F20 Series, User Manual

Page: 83 / 950

GD32F20x User Manual
83
The ADCs are clocked by the clock of APB2 divided by 2, 4, 6, 8, 12 or 16, which defined by
ADCPSC in RCU_CFG0.
The TIMERs are clocked by the clock divided from CK_APB2 and CK_APB1. The frequency
of TIMERs clock is equal to CK_APBx(APB prescaler is 1), twice the CK_APBx(APB
prescaler is not 1).
The USBFS is clocked by PLL, divided by 1, 1.5, 2, 2.5 which select by USBFSPSC bit in
configuration register 0 (RCU_CFG0).The USBFS clock must be 48MHz. These bits also
control the random analog generator (TRNG) clock (
≤
48 MHz). The TRNG is also clocked
by PLL, divided by 1, 1.5, 2, 2.5 which select by USBFSPSC bits.
The I2S is clocked by the clock of CK_SYS or PLL2*2 which defined by I2SxSEL bit in
RCU_CFG1 register.
The ENET TX/RX are clocked by External PIN (ENET_TX_CLK / ENET_RX_CLK), which
select by ENET_PHY_SEL bit in AFIO_PCF0 register.
The Ethernet MAC is clocked by the external PHY. If using the Ethernet module, it must keep
the AHB clock frequency at least 25 MHz.
The RTC is clocked by LXTAL clock or IRC40K clock or HXTAL clock divided by 128 which
select by RTCSRC bit in Backup Domain Control Register (RCU_BDCTL).
The FWDGT is clocked by IRC40K clock, which is forced on when FWDGT started.
5.2.2. Characteristics

3 to 25 MHz High Speed crystal oscillator (HXTAL) .

Internal 8 MHz RC oscillator (IRC8M).

32,768 Hz Low Speed crystal oscillator (LXTAL).

Internal 40 KHz RC oscillator (IRC40K).

PLL clock source can be HXTAL, IRC8M or PLL1.

HXTAL clock monitor.
5.2.3. Function overview
High speed crystal oscillator (HXTAL)
The High speed crystal oscillator (HXTAL), which has a frequency range from 3 to 25 MHz,
produces a highly accurate clock source for using as the system clock. A crystal with a specific
frequency must be connected and located close to the two HXTAL pins. The external resistor
and capacitor components connected to the crystal are necessary for proper oscillation.