GigaDevice Semiconductor GD32F20 Series, User Manual

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GD32F20x User Manual
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Figure 18-51. Normal mode, internal clock divided by 1
CK_TIMER
CEN
PSC_CLK = TIMER_CK
CNT_REG
Reload Pulse
17 18 19 20 21 22
update event generat e(UPG)
23 00 01 02 03 04 05 06
07
Update event (UPE)
 SMC [2:0] == 3’b111 (
external clock mode 0
). External input pin source
The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising
or falling edge on the external pin TIMERx_CI0/TIMERx_CI1. This mode can be selected by
setting SMC [2:0] to 0x7 and the TRGS [2:0] to 0x4, 0x5 or 0x6.
And, the counter prescaler can also be driven by rising edge on the internal trigger input pin
ITI0/1/2/3. This mode can be selected by setting SMC [2:0] to 0x7 and the TRGS [2:0] to 0x0,
0x1, 0x2 or 0x3.
 SMC1== 1’b1 (
external clock mode 1
). External input pin source (ETI)
The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising
or falling edge on the external pin ETI. This mode can be selected by setting the SMC1 bit in
the TIMERx_SMCFG register to 1. The other way to select the ETI signal as the clock source
is set the SMC [2:0] to 0x7 and the TRGS [2:0] to 0x7 respectively. Note that the ETI signal
is derived from the ETI pin sampled by a digital filter. When the clock source is selected to
come from the ETI signal, the Trigger Controller including the edge detection circuitry will
generate a clock pulse during each ETI signal rising edge to clock the counter prescaler.
Prescaler
The prescaler can divide the timer clock (TIMER_CK) to the counter clock (PSC_CLK by any
factor between 1 and 65536. It is controlled through prescaler register (TIMERx_PSC) which
can be changed on the go but be taken into account at the next update event.