GigaDevice Semiconductor GD32F20 Series, User Manual

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GD32F20x User Manual
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18.1.4. Function overview
Clock selection
The advanced timer has the capability of being clocked by either the TIMER_CK or an
alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]).

SMC [2:0] ==
3’b000. Internal clock CK_TIMER is selected as timer clock source which
is from module RCU.
The default clock source is the CK_TIMER for driving the counter prescaler when the slave
mode is disabled (SMC [2:0] == 3’b000). When the CEN is set, the CK_TIMER will be divided
by PSC value to generate PSC_CLK.
In this mode, the TIMER_CK, which drives counter’s prescaler to count, is equal to
CK_TIMER which is from RCU.
If the slave mode controller is enabled by setting SMC [2:0] in the TIMERx_SMCFG register
to an available value including 0x1, 0x2, 0x3 and 0x7, the prescaler is clocked by other clock
sources selected by the TRGS [2:0] in the TIMERx_SMCFG register, details as follows. When
the slave mode selection bits SMC [2:0] are set to 0x4, 0x5 or 0x6, the internal clock
TIMER_CK is the counter prescaler driving clock source.
Figure 18-2. Normal mode, internal clock divided by 1
CK_TIMER
CEN
PSC_CLK = TIMER_CK
CNT_REG
Reload Pulse
17 18 19 20 21 22
update event generat e(UPG)
23 00 01 02 03 04 05 06
07
Update event (UPE)
 SMC [2:0] == 3’b111 (
external clock mode 0
). External input pin is selected as timer clock
source
The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of
rising or falling edge on the external pin TIMERx_CH0/TIMERx_CH1. This mode can be
selected by setting SMC [2:0] to 0x7 and the TRGS [2:0] to 0x4, 0x5 or 0x6.
And, the counter prescaler can also be driven by rising edge on the internal trigger input pin