GigaDevice Semiconductor GD32F20 Series, User Manual

Page: 883 / 950

GD32F20x User Manual
883
Figure 28-5. HOST mode FIFO space in SRAM
Rx FIFO
Rx FIFO
Non-Periodic Tx FIFO
Periodic Tx FIFO
HNPTXRSAR[15:0]
HNPTXFD
HPTXFD
HPTXRSAR[15:0]
RXFD
Start: 0x00
End: 0x13F
USBFS provides a special register area for the internal data FIFO reading and writing. Figure
28-6. Host mode FIFO access register mapping describes the register memory area that
the data FIFO can access. The addresses in the figure are addressed in bytes. Each channel
has its own FIFO access register space, although all non-periodic channels share the same
FIFO and all the periodic channels also share the same FIFO. It is important for USBFS to
get which channel the current pushed packet belongs to, and the Rx FIFO which the packet
belongs to is also able to be accessed by using USBFS_GRSTATR/USBFS_GRSTATP
register.
Figure 28-6. Host mode FIFO access register mapping
CH0 FIFO Write/Read
CH1 FIFO Write/Read
1000h-1FFFh
CH7 FIFO Write/Read
...
2000h-2FFFh
8000h-8FFFh
Device mode
In device mode, the data FIFO is divided into several parts: 1 Rx FIFO, and 4 Tx FIFOs (one
for each IN endpoint). All the OUT endpoints share the Rx FIFO for receiving packets. The
size and start offset of these data FIFOs should be configured by using USBFS_GRFLEN
and USBFS_DIEPxTFLEN (
x=0…3) registers.
Figure 28-7. Device mode FIFO space in
SRAM describes the structure of these FIFOs in SRAM. The values in the figure are in term