GD32F20x User Manual
554
Figure 21-9. Timing diagram of quad read operation in Quad-SPI mode
D1[5]
D1[4]
D1[6]
D1[7]
D1[0]
D1[1]
D1[2]
D1[3]
SCK
MOSI
MISO
IO2
IO3
TBE
D2[4]
D2[6]
D2[7]
D2[0]
D2[1]
D2[2]
D2[3]
D2[5]
Software Writes
SPI_DATA
Hadware Sets TBE
RBNE
Software Reads
SPI_DATA
Software Writes
SPI_DATA
SPI disabling sequence
Different sequences are used to disable the SPI in different operation modes:
MFD SFD
Wait for the last RBNE flag and then receive the last data. Confirm that TBE=1 and TRANS=0.
At last, disable the SPI by clearing SPIEN bit.
MTU MTB STU STB
Write the last data into SPI_DATA and wait until the TBE flag is set and then wait until the
TRANS flag is cleared. Disable the SPI by clearing SPIEN bit.
MRU MRB
After getting the second last RBNE flag, read out this data and delay for a SCK clock time
and then, disable the SPI by clearing SPIEN bit. Wait until the last RBNE flag is set and read
out the last data.
SRU SRB
Application can disable the SPI when it doesn
’t want to receive data, and then wait until the
Summary of Contents for GD32F20 Series
Page 191: ...GD32F20x User Manual 191 Bits Fields Descriptions 31 0 TRNDATA 31 0 32 Bit Random data ...
Page 290: ...GD32F20x User Manual 290 conversion is ongoing ...
Page 325: ...GD32F20x User Manual 325 15 0 ALRM 15 0 RTC alarm value low ...
Page 385: ...GD32F20x User Manual 385 ...
Page 523: ...GD32F20x User Manual 523 clears AERR bit by writing 0 to it ...