GD32F20x User Manual
777
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
HBC1F[5:0]
Reserved
FLD
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Bits
Fields
Descriptions
31:14
Reserved
Must be kept at reset value
13:8
HBC1F[5:0]
Header bank of CAN1 filter
These bits are set and cleared by software to define the first bank for CAN1 filter.
Bank0 ~ Bank HBC1F-1 used to CAN0. Bank HBC1F ~ Bank27 used to CAN1.
When set 0, not bank used to CAN0. When set 28, not bank used to CAN1.
7:1
Reserved
Must be kept at reset value
0
FLD
Filter lock disable
0: Filter lock enable
1: Filter lock disable
26.4.18.
Filter mode configuration register (CAN_FMCFG)
Address offset: 0x204
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit). This register can be modified only when
FLD bit in CAN_FCTL register is set.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
FMOD27 FMOD26 FMOD25 FMOD24 FMOD23 FMOD22 FMOD21 FMOD20 FMOD19 FMOD18 FMOD17 FMOD16
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FMOD15 FMOD14 FMOD13 FMOD12 FMOD11 FMOD10
FMOD9
FMOD8
FMOD7
FMOD6
FMOD5
FMOD4
FMOD3
FMOD2
FMOD1
FMOD0
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Bits
Fields
Descriptions
31:28
Reserved
Must be kept at reset value
27:0
FMODx
Filter mode
0: Filter x with Mask mode
1: Filter x with List mode
26.4.19.
Filter scale configuration register (CAN_FSCFG)
Address offset: 0x20C
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit). This register can be modified only when
Summary of Contents for GD32F20 Series
Page 191: ...GD32F20x User Manual 191 Bits Fields Descriptions 31 0 TRNDATA 31 0 32 Bit Random data ...
Page 290: ...GD32F20x User Manual 290 conversion is ongoing ...
Page 325: ...GD32F20x User Manual 325 15 0 ALRM 15 0 RTC alarm value low ...
Page 385: ...GD32F20x User Manual 385 ...
Page 523: ...GD32F20x User Manual 523 clears AERR bit by writing 0 to it ...