GigaDevice Semiconductor GD32F20 Series, User Manual

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GD32F20x User Manual
722
precharge command is issued. The precharge command is used to deactivate an active row
in a particular bank or the active row in all banks. A precharge command must be issued
before activating a different row in the same bank. Active and precharge are automatically
issued by the EXMC, its correctness depends on memory dimension configurations discussed
previously, read and write timing diagram concerning automatic row activation and precharge
are depicted as follows.
Figure 25-35. Cross boundary read operation
Chip Enable
(EXMC_SDNEx)
Column Address
Strobe
(EXMC_NCAS)
Row Address
Strobe
(EXMC_NRAS)
Write Enable
(EXMC_SDNWE)
Data
(EXMC_D[31:0])
Clock
(EXMC_SDCLK)
Address
(EXMC_A[12:0])
Col
m
Col
m+1
Row
n+1
Col
m
Col
m+1
Col
m+2
Col
m
Col
m+1
Col
m
Col
m+1
Col
m+2
RPD = 3 RCD = 3 CL = 3
Precharge Active Row
Read
Command
Row n
Figure 25-36. Cross boundary write operation
Chip Enable
(EXMC_SDNEx)
Column Address
Strobe
(EXMC_NCAS)
Row Address
Strobe
(EXMC_NRAS)
Write Enable
(EXMC_SDNWE)
Data
(EXMC_D[31:0])
Clock
(EXMC_SDCLK)
Address
(EXMC_A[12:0])
Col
m
Col
m+1
Row
n+1
Col
m
Col
m+1
Col
m+2
Col
m
Col
m+1
Col
m
Col
m+1
Col
m+2
RPD = 3 RCD = 3
Precharge Active Row
Write
Command
Row n
The above diagrams depict read and write timing waveform when memory access crosses
row boundary, the following steps are preformed automatically:
1. Precharge the current active row.
2.
Next row’s activation.
3. Read/write access.