GigaDevice Semiconductor GD32F20 Series, User Manual

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GD32F20x User Manual
690
Timing
model
Extend
mode
Mode description
Write timing
parameter
Read timing
parameter
Mode SM 0 NOR Flash address/data mux
DLAT
CKDIV
DLAT
CKDIV
As shown in Table 25-7. EXMC_timing models , EXMC NOR Flash / PSRAM controller
provides a variety of timing model, users can modify those parameters listed in Table 25-6.
NOR / PSRAM controller timing parameters to satisfy different external memory type and
user’s requirements. When extended mode is enabled via the EXMODEN bit in
EXMC_SNCTLx register, different timing patterns for read and write access could be
generated independently according to EXMC_SNTCFGx and EXMC_SNWTCFGx register’s
configuration.
Asynchronous access timing diagram
Mode 1 - SRAM/CRAM
Figure 25-7. Mode 1 read access
Address
(EXMC_A[25:0])
Byte Lane Select
(EXMC_NBL[1:0])
Chip Enable
(EXMC_NEx)
Output Enable
(EXMC_NOE)
Write Enable
(EXMC_NWE)
Data
(EXMC_D[15:0])
Memory Output
Address Setup Time
(ASET HCLK)
Data Setup Time
(DSET HCLK)
Figure 25-8. Mode 1 write access
Address
(EXMC_A[25:0])
Byte Lane Select
(EXMC_NBL[1:0])
Chip Enable
(EXMC_NEx)
Output Enable
(EXMC_NOE)
Write Enable
(EXMC_NWE)
Data
(EXMC_D[15:0])
Address Setup Time
(ASET HCLK)
Data Setup Time
(DSET HCLK)
EXMC Output
1 HCLK
Table 25-8. Mode 1 related registers configuration
EXMC_SNCTLx