GD32F20x User Manual
20
List of Figures
Figure 1-2. GD32F20x Connectivity line series system architecture
...................................................... 34
Figure 2-1. Process of page erase operation
.............................................................................................. 47
Figure 2-2. Process of mass erase operation
............................................................................................. 48
Figure 2-3. Process of word program operation
........................................................................................ 50
Figure 3-1. Power supply overview
Figure 3-2. Waveform of the POR/PDR
Figure 3-3. Waveform of the LVD threshold
................................................................................................ 66
Figure 5-1. The system reset circuit
Figure 5-3. HXTAL clock source
Figure 6-1. Block diagram of EXTI
Figure 7-1. The basic structure of a standard I/O and five-volt tolerant I/O Port
................................ 135
Figure 7-2. Input configuration
Figure 7-3. Output configuration
Figure 7-4. Analog configuration
Figure 7-5. Alternate function configuration
............................................................................................. 139
Figure 8-1. Block diagram of CRC calculation unit
.................................................................................. 183
Figure 9-1. TRNG block diagram
Figure 10-1. DATAM No swapping and Half-word swapping
................................................................. 193
Figure 10-2. DATAM Byte swapping and Bit swapping
........................................................................... 194
Figure 10-4. DES/TDES ECB encryption
Figure 10-5. DES/TDES ECB decryption
Figure 10-6. DES/TDES CBC encryption
Figure 10-7. DES/TDES CBC decryption
Figure 10-8. AES ECB encryption
Figure 10-9. AES ECB decryption
Figure 10-10. AES CBC encryption
Figure 10-11. AES CBC decryption
Figure 10-12. Counter block structure
Figure 10-13. AES CTR encryption/decryption
......................................................................................... 202
Figure 11-1. DATAM No swapping and Half-word swapping
................................................................. 218
Figure 11-2. DATAM Byte swapping and Bit swapping
........................................................................... 218
Figure 11-3. HAU block diagram
Figure 12-1. Block diagram of DMA
Figure 12-2. Handshake mechanism
Figure 12-3. DMA interrupt logic
Figure 12-4. DMA0 request mapping
Figure 12-5. DMA1 request mapping
Summary of Contents for GD32F20 Series
Page 191: ...GD32F20x User Manual 191 Bits Fields Descriptions 31 0 TRNDATA 31 0 32 Bit Random data ...
Page 290: ...GD32F20x User Manual 290 conversion is ongoing ...
Page 325: ...GD32F20x User Manual 325 15 0 ALRM 15 0 RTC alarm value low ...
Page 385: ...GD32F20x User Manual 385 ...
Page 523: ...GD32F20x User Manual 523 clears AERR bit by writing 0 to it ...