GD32F20x User Manual
359
18.1.5.
Register definition
TIMER0 start address: 0x4001 2C00
TIMER7 start address: 0x4001 3400
Control register 0 (TIMERx_CTL0)
Address offset: 0x00
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CKDIV[1:0]
ARSE
CAM[1:0]
DIR
SPM
UPS
UPDIS
CEN
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:10
Reserved
Must be kept at reset value.
9:8
CKDIV[1:0]
Clock division
The CKDIV bits can be configured by software to specify division ratio between
the timer clock (TIMER_CK) and the dead-time and sampling clock (DTS), which
is used by the dead-time generators and the digital filters.
00: f
DTS
=f
TIMER_CK
01: f
DTS
= f
TIMER_CK
/2
10: f
DTS
= f
TIMER_CK
/4
11: Reserved
7
ARSE
Auto-reload shadow enable
0: The shadow register for TIMERx_CAR register is disabled
1: The shadow register for TIMERx_CAR register is enabled
6:5
CAM[1:0]
Counter aligns mode selection
00: No center-aligned mode (edge-aligned mode). The direction of the counter is
specified by the DIR bit.
01: Center-aligned and counting down assert mode. The counter counts under
center-aligned and channel is configured in output mode (CHxMS=00 in
TIMERx_CHCTL0 register). Only when the counter is counting down, compare
interrupt flag of channels can be set.
10: Center-aligned and counting up assert mode. The counter counts under
center-aligned and channel is configured in output mode (CHxMS=00 in
TIMERx_CHCTL0 register). Only when the counter is counting up, compare
interrupt flag of channels can be set.
Summary of Contents for GD32F20 Series
Page 191: ...GD32F20x User Manual 191 Bits Fields Descriptions 31 0 TRNDATA 31 0 32 Bit Random data ...
Page 290: ...GD32F20x User Manual 290 conversion is ongoing ...
Page 325: ...GD32F20x User Manual 325 15 0 ALRM 15 0 RTC alarm value low ...
Page 385: ...GD32F20x User Manual 385 ...
Page 523: ...GD32F20x User Manual 523 clears AERR bit by writing 0 to it ...