GigaDevice Semiconductor GD32F20 Series, User Manual

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GD32F20x User Manual
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This register has to be accessed by word (32-bit)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DI[31:16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DI[15:0]
rw
Bits Fields Descriptions
31:0 DI[31:0] Message data input
When write to these registers, the current content pushed to IN FIFO and new value
updates. When read, returns the current content.
11.6.3. HAU configuration register (HAU_CFG)
Address offset: 0x08
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved CALEN Reserved VBL[4:0]
w rw
Bits Fields Descriptions
31:9 Reserved Must keep the reset value
8 CALEN Digest calculation enable
0: No calculation
1: Start data padding with VBL prepared previously. Start the calculation of the last
digest
Note: reading this bit always returns 0
7:5 Reserved Must keep the reset value
4:0 VBL[4:0] Valid bits length in the last word
0x00: All 32 bits of the last data written to HAU_DI after data swapping are valid.
0x01: Only bit [31] of the last data written to HAU_DI after data swapping are valid.
0x02: Only bits [31:30] of the last data written to HAU_DI after data swapping are
valid.
0x03: Only bits [31:29] of the last data written to HAU_DI after data swapping are
valid.