GigaDevice Semiconductor GD32F20 Series, User Manual

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GD32F20x User Manual
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PLLTSEL PLLTRPSC[2:0] Reserved TLIPSC[1:0]
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PLLTMF[8:0] PLLTPSC[5:0]
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Bits Fields Descriptions
31 PLLTSEL PLLT clock source select
This bit can be written only when PLLT is disabled
0: select CK_IRC8M
1: select CK_HXTAL
30:28 PLLTRPSC[2:0] PLLTR prescaler selection
Set and reset by software to control the TLI clock frequency.
These bits should be written when the PLLT is disabled.
PLLTR clock frequency = VCO frequency / PLLTRPSC ,
with 2 ≤ PLLTRPSC ≤ 7
000: PLLTRPSC = 0, wrong configuration
001: PLLTRPSC = 1, wrong configuration
010: PLLTRPSC = 2
...
111: PLLTRPSC = 7
27:18 Reserved Must be kept at reset value
17:16 TLIPSC[1:0] TLI prescaler selection
These bits are set and cleared by software to control the frequency of CK_TLI.
They should be written only if PLLT is disabled.
CK_TLI frequency = f(PLLTR) / TLIPS
C with 2 ≤ TLIPSC≤ 16
00: TLIPSC = 2
01: TLIPSC = 4
10: TLIPSC = 8
11: TLIPSC = 16
15 Reserved Must be kept at reset value
14:6 PLLTMF[8:0] PLLT multiply factor for VCO
Set and reset by software to control the multiplication factor of the VCO.
These bits should be written when the PLLT is disabled.
Only half-word and word accesses are allowed to write these bits.
VCO output frequency = VCO input frequency x PLLTMF
with 49 ≤ PLLTMF≤ 432
000000000: PLLTMF = 0, wrong configuration
000000001: PLLTMF = 1, wrong configuration
......
000110000: PLLTMF = 48, wrong configuration
000110001: PLLTMF = 49
...