GigaDevice Semiconductor GD32F20 Series, User Manual

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GD32F20x User Manual
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PIPED[1:0] BRSTRD SDCLK[1:0] WPEN CL[1:0] NBK SDW[1:0] RAW[1:0] CAW[1:0]
rw rw rw rw rw rw rw rw rw
Bits Fields Descriptions
31:15 Reserved Must be kept at reset value
14:13 PIPED[1:0] Pipeline delay
These bits specify the delay for reading data after CAS latency in HCLK clock
cycles.
00: 0 HCLK clock cycle delay
01: 1 HCLK clock cycle delay
10: 2 HCLK clock cycle delay
11: reserved
Note: The corresponding bits in the EXMC_SDCTL1 register are reserved.
12 BRSTRD Burst read
When this bit is set, The SDRAM controller anticipates the next read commands
during the CAS latency and stores data in the Read FIFO.
0: burst read disabled
1: burst read enabled
Note: The corresponding bits in the EXMC_SDCTL1 register are reserved.
11:10 SDCLK[1:0] SDRAM clock configuration
These bits specifies the SDRAM clock period for both SDRAM devices. The
memory clock should be disabled before change, and the SDRAM memory must
be re-initialized after this configuration is changed.
00: SDCLK memory clock disabled
01: Reserved
10: SDCLK memory period = 2 x HCLK periods
11: SDCLK memory period = 3 x HCLK periods
Note: The corresponding bits in the EXMC_SDCTL1 register are reserved.
9 WPEN Write protection enable
This bit enables the write protection function.
0: Disable write protection, write accesses allowed
1: Enable write protection, write accesses ignored
8:7 CL[1:0] CAS Latency
This bits sets specifies SDRAM CAS latency in SDRAM memory clock cycle unit
00: reserved, do not use.
01: 1 cycle
10: 2 cycles
11: 3 cycles
6 NBK Number of banks
This bit specifies the number of internal banks.