GD32F20x User Manual
573
received.
11
FF16
Data frame format
0: 8-bit data frame format
1: 16-bit data frame format
10
RO
Receive only
When BDEN is cleared, this bit determines the direction of transfer.
0: Full-duplex
1: Receive-only
9
SWNSSEN
NSS Software Mode Selection
0: NSS hardware mode. The NSS level depends on NSS pin.
1: NSS software mode. The NSS level depends on SWNSS bit.
8
SWNSS
NSS Pin Selection In NSS Software Mode
0: NSS pin is pulled low
1: NSS pin is pulled high
This bit has an effect only when the SWNSSEN bit is set.
7
LF
LSB First Mode
0: Transmit MSB first
1: Transmit LSB first
6
SPIEN
SPI Enable
0: SPI peripheral is disabled
1: SPI peripheral is enabled
5:3
PSC[2:0]
Master Clock Prescaler Selection
000: PCLK/2 100: PCLK/32
001: PCLK/4 101: PCLK/64
010: PCLK/8 110: PCLK/128
011: PCLK/16 111: PCLK/256
PCLK means PCLK2 when using SPI0 or PCLK1 when using SPI1 and SPI2.
2
MSTMOD
Master Mode Enable
0: Slave mode
1: Master mode
1
CKPL
Clock Polarity Selection
0: CLK pin is pulled low when SPI is idle
1: CLK pin is pulled high when SPI is idle
0
CKPH
Clock Phase Selection
0: Capture the first data at the first clock transition.
1: Capture the first data at the second clock transition
Summary of Contents for GD32F20 Series
Page 191: ...GD32F20x User Manual 191 Bits Fields Descriptions 31 0 TRNDATA 31 0 32 Bit Random data ...
Page 290: ...GD32F20x User Manual 290 conversion is ongoing ...
Page 325: ...GD32F20x User Manual 325 15 0 ALRM 15 0 RTC alarm value low ...
Page 385: ...GD32F20x User Manual 385 ...
Page 523: ...GD32F20x User Manual 523 clears AERR bit by writing 0 to it ...