GigaDevice Semiconductor GD32F20 Series User Manual Download Page 272

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GD32F20x User Manual

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of both ADCs are continuously converted. The behavior of follow-up fast mode shows in the

Figure 14-18. Follow-up fast mode on 1 channel in continuous conversion mode

After an EOC interrupt is generated by ADC0 in case of setting the EOCIE bit, we can use a

32-bit DMA, which transfers to SRAM the ADC_RDATA 32-bit register containing the ADC1

converted data in the upper half word and the ADC0 converted data in the lower half word.

Note:

The maximum sampling time allowed is <7 ADCCLK cycles to avoid the overlap

between ADC0 and ADC1 sampling phases in the event that they convert the same channel.

Figure 14-18. Follow-up fast mode on 1 channel in continuous conversion mode

CH1

ADC0

ADC1

Regular

trigger

Sample

Convert

EOC(ADC1 )

EOC(ADC0)

CH1

7 ADCCLK cycles

14.5.5.

Follow-up slow mode

This mode can be running on the regular channel group (usually one channel). The source of

external trigger comes from the regular channel MUX of ADC0(selected by the ETSRC[2:0]

bits in the ADC_CTL1 register).When the trigger occurs, ADC1 runs immediately, ADC0 runs

after 14 ADC clock cycles, after the second 14 ADC clock cycles the ADC1 runs again.

Continuous mode

can’t be used in this mode, because it continuously converts the regular

channel. The behavior of follow-up slow mode shows in the

Figure 14-19. Follow-up slow

mode on 1 channel

After an EOC interrupt is generated by ADC0 (if enabled through the EOCIE bit), we can use

a 32-bit DMA, which transfers to SRAM the ADC_RDATA 32-bit register containing the ADC1

converted data in the upper half-word and the ADC0 converted data in the lower half-word.

Note:

1. The maximum sampling time allowed is <14 ADCCLK cycles to avoid the overlap between

ADC0 and ADC1 sampling phases in the event that they convert the same channel.

2. For both the fast and follow-up slow mode, we must ensure that no external trigger for

inserted channel occurs.

Summary of Contents for GD32F20 Series

Page 1: ...GigaDevice Semiconductor Inc GD32F20x ARM Cortex M3 32 bit MCU User Manual Revision 2 2 Oct 2019 ...

Page 2: ...ation registers 42 2 Flash memory controller FMC 44 2 1 Overview 44 2 2 Characteristics 44 2 3 Function overview 44 2 3 1 Flash memory architecture 44 2 3 2 Read operations 45 2 3 3 Unlock the FMC_CTLx registers 45 2 3 4 Page erase 46 2 3 5 Mass erase 47 2 3 6 Main flash programming 49 2 3 7 Option bytes Erase 50 2 3 8 Option bytes modify 51 2 3 9 Option bytes description 51 2 3 10 Page erase prog...

Page 3: ... VDDA power domain 65 3 3 3 1 2V power domain 67 3 3 4 Power saving modes 67 3 4 Register definition 70 3 4 1 Control register PMU_CTL 70 3 4 2 Control and status register PMU_CS 71 4 Backup registers BKP 73 4 1 Overview 73 4 2 Characteristics 73 4 3 Function overview 73 4 3 1 RTC clock calibration 73 4 3 2 Tamper0 detection 74 4 3 3 Tamper1 detection 74 16 1 1 Waveform detection 74 4 4 Register d...

Page 4: ...nable register RCU_ADDAPB2EN 116 5 3 16 APB1 additional enable register RCU_ADDAPB1EN 117 5 3 17 AHB2 reset register RCU_AHB2RST 117 5 3 18 APB2 additional reset register RCU_ADDAPB2RST 118 5 3 19 APB1 additional reset register RCU_ADDAPB1RST 119 5 3 20 Configuration register 2 RCU_ CFG2 120 5 3 21 PLLT control register RCU_PLLTCTL 121 5 3 22 PLLT interrupt register RCU_PLLTINT 122 5 3 23 PLLT con...

Page 5: ...mapping 146 7 4 9 CAN AF remapping 146 7 4 10 Ethernet AF remapping 147 7 4 11 DCI AF remapping 148 7 4 12 TLI AF remapping 148 7 4 13 CLK pins AF remapping 149 7 5 Register definition 151 7 5 1 Port control register 0 GPIOx_CTL0 x A I 151 7 5 2 Port control register 1 GPIOx_CTL1 x A I 153 7 5 3 Port input status register GPIOx_ISTAT x A I 154 7 5 4 Port output control register GPIOx_OCTL x A I 15...

Page 6: ...haracteristics 187 9 3 Function overview 187 9 3 1 Operation flow 188 9 3 2 Error flags 188 9 4 Register definition 189 9 4 1 Control register TRNG_CTL 189 9 4 2 Status register TRNG_STAT 189 9 4 3 Data register TRNG_DATA 190 10 Cryptographic Acceleration Unit CAU 192 10 1 Overview 192 10 2 Characteristics 192 10 3 CAU data type and initialization vectors 193 10 3 1 Data type 193 10 3 2 Initializa...

Page 7: ... 4 2 Digest computing 220 11 4 3 Hash mode 221 11 4 4 HMAC mode 221 11 5 HAU interrupt 221 11 6 Register definition 223 11 6 1 HAU control register HAU_CTL 223 11 6 2 HAU data input register HAU_DI 224 11 6 3 HAU configuration register HAU_CFG 225 11 6 4 HAU data output register HAU_DO0 7 226 11 6 5 HAU interrupt enable register HAU_INTEN 228 11 6 6 HAU status and interrupt flag register HAU_STAT ...

Page 8: ... function overview 247 13 3 1 Debug support for power saving mode 247 13 3 2 Debug support for TIMER I2C WWDGT FWDGT and CAN 248 13 4 Register definition 249 13 4 1 ID code register DBG_ID 249 13 4 2 Control register DBG_CTL 249 14 Analog to digital converter ADC 253 14 1 Overview 253 14 2 Characteristics 253 14 3 Pins and internal signals 254 14 4 Function overview 255 14 4 1 Calibration CLB 255 ...

Page 9: ...ster x ADC_IOFFx x 0 3 283 14 7 7 Watchdog high threshold register ADC_WDHT 284 14 7 8 Watchdog low threshold register ADC_WDLT 284 14 7 9 Regular sequence register 0 ADC_RSQ0 285 14 7 10 Regular sequence register 1 ADC_RSQ1 285 14 7 11 Regular sequence register 2 ADC_RSQ2 286 14 7 12 Inserted sequence register ADC_ISQ 286 14 7 13 Inserted data register x ADC_IDATAx x 0 3 287 14 7 14 Regular data ...

Page 10: ... DAC1 data output register DAC1_DO 304 16 Watchdog timer WDGT 305 16 1 Free watchdog timer FWDGT 305 16 1 1 Overview 305 16 1 2 Charateristics 305 16 1 3 Function overview 305 16 1 4 Register definition 308 16 2 Window watchdog timer WWDGT 311 16 2 1 Overview 311 16 2 2 Charateristics 311 16 2 3 Function overview 311 16 2 4 Register definition 314 17 Real time Clock RTC 316 17 1 Overview 316 17 2 ...

Page 11: ... 3 Block diagram 427 18 3 4 Function overview 427 18 3 5 Register definition 442 18 4 General level2 timer TIMERx x 9 10 12 13 455 18 4 1 Overview 455 18 4 2 Characteristics 455 18 4 3 Block diagram 455 18 4 4 Function overview 456 18 4 5 Register definition 467 18 5 Basic timer TIMERx x 5 6 478 18 5 1 Overview 478 18 5 2 Characteristics 478 18 5 3 Block diagram 478 18 5 4 Function overview 479 18...

Page 12: ...out register USART_RT 515 19 4 10 Status register 1 USART_STAT1 515 20 Inter integrated circuit interface I2C 517 20 1 Overview 517 20 2 Characteristics 517 20 3 Function overview 517 20 3 1 SDA and SCL lines 518 20 3 2 Data validation 519 20 3 3 START and STOP condition 519 20 3 4 Clock synchronization 519 20 3 5 Arbitration 520 20 3 6 I2C communication flow 521 20 3 7 Programming model 521 20 3 ...

Page 13: ...5 21 5 5 CRC function 555 21 6 SPI interrupts 555 21 6 1 Status flags 555 21 6 2 Error conditions 556 21 7 I2S block diagram 557 21 8 I2S signal description 557 21 9 I2S function overview 558 21 9 1 I2S audio standards 558 21 9 2 I2S clock 566 21 9 3 Operation 567 21 9 4 DMA function 570 21 10 I2S interrupts 570 21 10 1 Status flags 570 21 10 2 Error conditions 570 21 11 Register definition 572 21...

Page 14: ...r1 DCI_STAT1 589 22 7 4 Interrupt enable register DCI_INTEN 589 22 7 5 Interrupt flag register DCI_INTF 590 22 7 6 Interrupt flag clear register DCI_INTC 591 22 7 7 Synchronization codes register DCI_SC 591 22 7 8 Synchronization codes unmask register DCI_SCUMSK 592 22 7 9 Cropping window start position register DCI_CWSPOS 592 22 7 10 Cropping window size register DCI_CWSZ 593 22 7 11 DATA registe...

Page 15: ...color key register TLI_LxCKEY 611 23 6 18 Layer x packeted pixel format register TLI_LxPPF 611 23 6 19 Layer x specified alpha register TLI_LxSA 612 23 6 20 Layer x default color register TLI_LxDC 612 23 6 21 Layer x blending register TLI_LxBLEND 613 23 6 22 Layer x frame base address register TLI_LxFBADDR 614 23 6 23 Layer x frame line length register TLI_LxFLLEN 614 23 6 24 Layer x frame total l...

Page 16: ... 8 Data length register SDIO_DATALEN 671 24 8 9 Data control register SDIO_DATACTL 672 24 8 10 Data counter register SDIO_DATACNT 672 24 8 11 Status register SDIO_STAT 674 24 8 12 Interrupt clear register SDIO_INTC 675 24 8 13 Interrupt enable register SDIO_INTEN 676 24 8 14 FIFO counter register SDIO_FIFOCNT 678 24 8 15 FIFO data register SDIO_FIFO 679 25 External memory controller EXMC 680 25 1 ...

Page 17: ...26 4 10 Transmit mailbox property register CAN_TMPx x 0 2 772 26 4 11 Transmit mailbox data0 register CAN_TMDATA0x x 0 2 773 26 4 12 Transmit mailbox data1 register CAN_TMDATA1x x 0 2 774 26 4 13 Receive FIFO mailbox identifier register CAN_RFIFOMIx x 0 1 774 26 4 14 Receive FIFO mailbox property register CAN_RFIFOMPx x 0 1 775 26 4 15 Receive FIFO mailbox data0 register CAN_RFIFOMDATA0x x 0 1 775...

Page 18: ...ter ENET_MAC_ADDR0H 844 27 4 15 MAC address 0 low register ENET_MAC_ADDR0L 845 27 4 16 MAC address 1 high register ENET_MAC_ADDR1H 845 27 4 17 MAC address 1 low register ENET_MAC_ADDR1L 846 27 4 18 MAC address 2 high register ENET_MAC_ADDR2H 847 27 4 19 MAC address 2 low register ENET_MAC_ADDR2L 847 27 4 20 MAC address 3 high register ENET_MAC_ADDR3H 848 27 4 21 MAC address 3 low register ENET_MAC...

Page 19: ...ET_DMA_CTL 867 27 4 49 DMA interrupt enable register ENET_DMA_INTEN 870 27 4 50 DMA missed frame and buffer overflow counter register ENET_DMA_MFBOCNT 872 27 4 51 DMA current transmit descriptor address register ENET_DMA_CTDADDR 873 27 4 52 DMA current receive descriptor address register ENET_DMA_CRDADDR 873 27 4 53 DMA current transmit buffer address register ENET_DMA_CTBADDR 874 27 4 54 DMA curr...

Page 20: ...igure 8 1 Block diagram of CRC calculation unit 183 Figure 9 1 TRNG block diagram 187 Figure 10 1 DATAM No swapping and Half word swapping 193 Figure 10 2 DATAM Byte swapping and Bit swapping 194 Figure 10 3 CAU diagram 195 Figure 10 4 DES TDES ECB encryption 196 Figure 10 5 DES TDES ECB decryption 197 Figure 10 6 DES TDES CBC encryption 198 Figure 10 7 DES TDES CBC decryption 199 Figure 10 8 AES ...

Page 21: ... in discontinuous mode 274 Figure 14 22 Regular parallel trigger rotation mode 274 Figure 14 23 Trigger occurs during inserted conversion 275 Figure 14 24 Follow up single channel with inserted sequence CH1 CH2 275 Figure 15 1 DAC block diagram 292 Figure 15 2 DAC LFSR algorithm 294 Figure 15 3 DAC triangle noise wave 294 Figure 16 1 Free watchdog block diagram 306 Figure 16 2 Window watchdog time...

Page 22: ...k divided by 1 388 Figure 18 34 Counter timing diagram with prescaler division change from 1 to 2 389 Figure 18 35 Up counter timechart PSC 0 1 390 Figure 18 36 Up counter timechart change TIMERx_CAR on the go 391 Figure 18 37 Down counter timechart PSC 0 1 392 Figure 18 38 Down counter timechart change TIMERx_CAR on the go 392 Figure 18 39 Center aligned counter timechart 394 Figure 18 40 Input c...

Page 23: ...Counter timing diagram with prescaler division change from 1 to 2 480 Figure 18 79 Up counter timechart PSC 0 1 481 Figure 18 80 Up counter timechart change TIMERx_CAR on the go 481 Figure 19 1 USART module block diagram 490 Figure 19 2 USART character frame 8 bits data and 1 stop bit 490 Figure 19 3 USART transmit procedure 492 Figure 19 4 Oversampling method of a receive frame bit 493 Figure 19 ...

Page 24: ...d timing diagram DTLEN 10 CHLEN 1 CKPL 1 559 Figure 21 15 I2S Phillips standard timing diagram DTLEN 01 CHLEN 1 CKPL 0 559 Figure 21 16 I2S Phillips standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 559 Figure 21 17 I2S Phillips standard timing diagram DTLEN 00 CHLEN 1 CKPL 0 560 Figure 21 18 I2S Phillips standard timing diagram DTLEN 00 CHLEN 1 CKPL 1 560 Figure 21 19 MSB justified standard timing ...

Page 25: ...ynchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 0 565 Figure 21 44 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 1 565 Figure 21 45 PCM standard long frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 0 565 Figure 21 46 PCM standard long frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 1 565 Figure 21 47 Block diagram of I2S ...

Page 26: ...94 Figure 25 13 Mode B write access 694 Figure 25 14 Mode C read access 695 Figure 25 15 Mode C write access 696 Figure 25 16 Mode D read access 697 Figure 25 17 Mode D write access 697 Figure 25 18 Multiplex mode read access 699 Figure 25 19 Multiplex mode write access 699 Figure 25 20 Read access timing diagram under async wait signal assertion 701 Figure 25 21 Write access timing diagram under ...

Page 27: ... signals 785 Figure 27 4 Media independent interface signals 786 Figure 27 5 Reduced media independent interface signals 788 Figure 27 6 Wakeup frame filter register 802 Figure 27 7 System time update using the fine correction method 805 Figure 27 8 Descriptor ring and chain structure 809 Figure 27 9 Transmit descriptor 815 Figure 27 10 Receive descriptor 822 Figure 27 11 MAC interrupt scheme 830 ...

Page 28: ...on AF remapping 141 Table 7 8 TIMER0 alternate function remapping 142 Table 7 9 TIMER1 alternate function remapping 142 Table 7 10 TIMER2 alternate function remapping 142 Table 7 11 TIMER3 alternate function remapping 142 Table 7 12 TIMER4 alternate function remapping 143 Table 7 13 TIMER7 alternate function remapping 143 Table 7 14 TIMER8 alternate function remapping 1 143 Table 7 15 TIMER9 alter...

Page 29: ...ADC1 265 Table 14 5 External trigger for regular channels for ADC2 265 Table 14 6 External trigger for inserted channels for ADC2 265 Table 14 7 tCONV timings depending on resolution 267 Table 14 8 Maximum output results vs N and M Grayed values indicates truncation 268 Table 15 1 DAC pins 292 Table 15 2 External triggers of DAC 293 Table 16 1 Min max FWDGT timeout period at 40 kHz IRC40K 306 Tabl...

Page 30: ...ented read commands class 2 632 Table 24 6 Stream read commands class 1 and stream write commands class 3 633 Table 24 7 Block Oriented write commands class 4 633 Table 24 8 Erase commands class 5 634 Table 24 9 Block oriented write protection commands class 6 635 Table 24 10 Lock card class 7 635 Table 24 11 Application specific commands class 8 636 Table 24 12 I O mode commands class 9 637 Table...

Page 31: ...on 699 Table 25 14 Timing configurations of synchronous multiplexed read mode 703 Table 25 15 Timing configurations of synchronous multiplexed write mode 704 Table 25 16 SPI QPI interface 705 Table 25 17 8 bit or 16 bit NAND interface signal 708 Table 25 18 16 bit PC card interface signal 708 Table 25 19 Bank1 2 3 of EXMC support the memory and access mode 708 Table 25 20 NAND flash or PC card pro...

Page 32: ... extendable 1 1 ARM Cortex M3 processor The Cortex M3 processor is a general purpose 32 bit processor core which is suitable for microcontrollers with high performance and low power consumption It offers many new features such as Thumb 2 instruction sets hardware divider low latency interrupt respond time atomic bit banding access and multiple buses for simultaneous accesses The Cortex M3 processo...

Page 33: ...x1FFF FFFF to the Cortex M3 core The DCode bus is used for loading storing data and also for debug access of the Code region Similarly the System bus is used for instruction vector fetches data loading storing and debugging access of the system regions The System regions include the internal SRAM region the external memory region and the Peripheral region The AHB matrix consists of eight slaves in...

Page 34: ...erals CAU HAU TRNG DCI DMA0 7 chs Master TLI SAR ADC Powered By VDDA ARM Cortex M3 Processor Fmax 120MHz SW JTAG System DCode ICode AHB Matrix APB2 Fmax 120MHz APB1 Fmax 60MHz SRAM0 SRAM1 SRAM2 Slave Slave Slave Slave AHB1 Peripherals SDIO CRC RCU USB FS DMA1 7 chs Master GPIOG USART5 GPIOH GPIOI USART1 2 UART3 4 UART6 7 I2C0 I2C1 I2C2 1 3 Memory map The ARM Cortex M3 processor is structured in Ha...

Page 35: ... by AHB1 peripherals And the address region from 0x5004 0000 to 0x5FFF FFFF is used by AHB2 peripherals Table 1 1 Memory map of GD32F20x devices Pre defined Regions Bus Address Peripherals External RAM AHB 0xC000 0000 0xDFFF FFFF EXMC SDRAM 0xA000 0000 0xA000 0FFF Reserved 0x9000 0000 0x9FFF FFFF EXMC PC CARD 0x7000 0000 0x8FFF FFFF EXMC NAND 0x6000 0000 0x6FFF FFFF EXMC NOR PSRAM SQPI PSRAM Perip...

Page 36: ... 0x4001 7C00 0x4001 7FFF Reserved 0x4001 7800 0x4001 7BFF Port I 0x4001 7400 0x4001 77FF Port H 0x4001 7000 0x4001 73FF USART5 0x4001 6C00 0x4001 6FFF Reserved 0x4001 6800 0x4001 6BFF TLI 0x4001 5C00 0x4001 67FF Reserved 0x4001 5800 0x4001 5BFF Reserved 0x4001 5400 0x4001 57FF TIMER10 0x4001 5000 0x4001 53FF TIMER9 0x4001 4C00 0x4001 4FFF TIMER8 0x4001 4800 0x4001 4BFF Reserved 0x4001 4400 0x4001 ...

Page 37: ...00 0x4000 67FF CAN0 0x4000 5C00 0x4000 63FF USB CAN shared 0x4000 5800 0x4000 5BFF I2C1 0x4000 5400 0x4000 57FF I2C0 0x4000 5000 0x4000 53FF UART4 0x4000 4C00 0x4000 4FFF UART3 0x4000 4800 0x4000 4BFF USART2 0x4000 4400 0x4000 47FF USART1 0x4000 4000 0x4000 43FF Reserved 0x4000 3C00 0x4000 3FFF SPI2 0x4000 3800 0x4000 3BFF SPI1 0x4000 3400 0x4000 37FF Reserved 0x4000 3000 0x4000 33FF FWDGT 0x4000 ...

Page 38: ... FFFF Reserved 0x0800 0000 0x082F FFFF Main Flash 0x0030 0000 0x07FF FFFF Aliased to Main Flash or Boot loader 0x0010 0000 0x002F FFFF 0x0002 0000 0x000F FFFF 0x0000 0000 0x0001 FFFF 1 3 1 Bit banding In order to reduce the time of read modify write operations the Cortex M3 processor provides a bit banding function to perform a single atomic bit operation The memory map includes two bit band regio...

Page 39: ...ously The location and the capacity of them are shown in Table 1 2 Each block of SRAM Table 1 2 Each block of SRAM Block Capacity Location SRAM0 112KB 0x2000 0000 0x2001 BFFF SRAM1 16KB 0x2001 C000 0x2001 FFFF SRAM2 256KB 0x2002 0000 0x2005 FFFF 1 3 3 On chip Flash memory The GD32F20x series of devices provide up to 3072 KB of on chip flash memory Read accesses can be performed 32 bits per cycle w...

Page 40: ...ated in the System memory which is used to reprogram the Flash memory In GD32F20x devices the boot loader can be activated through the USART0 interface GD32F2 MCU embedded bootloader supports multi interfaces to update the Flash memory There will be one or two USART ports and standard USB port can be used on GD32F205xx and GD32F207xx connectivity line products The details are shown in the followin...

Page 41: ...ates 32 Kbytes 15 0 FLASH_SIZE 15 0 Flash memory size The value indicates the Flash memory size of the device in Kbytes Example 0x0020 indicates 32 Kbytes 1 5 2 Unique device ID 96 bits Base address 0x1FFF F7E8 The value is factory programmed and can never be altered by user This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNIQUE_ID 31 16 r 15 14 13 1...

Page 42: ...6 UNIQUE_ID 95 80 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNIQUE_ID 79 64 r Bits Fields Descriptions 31 0 UNIQUE_ID 95 64 Unique device ID 1 6 System configuration registers Base address 0x4002 103C This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CEE Reserved rw Bits Fields Descriptions 31 8 Res...

Page 43: ...GD32F20x User Manual 43 6 0 Reserved Must be kept at reset value Note Only bit 7 can be read modify write other bits are not permitted ...

Page 44: ...20x_CL with flash size more than 512KB Bank0 is used for the first 512KB and bank1 is for the rest capacity Only bank0 is adopted for GD32F20x_CL with flash no more than 512KB The flash page size is 2KB for bank0 4KB for bank1 Word half word programming page erase and mass erase operation 16B option bytes block for user application requirements Option bytes are uploaded to the option byte control ...

Page 45: ...TLx registers After reset the FMC_CTL0 register are not accessible in write mode and the LK bit in FMC_CTL0 register is 1 An unlocking sequence consists of two write operations to the FMC_KEY0 register to open the access to the FMC_CTL0 register The two write operations are writing 0x45670123 and 0xCDEF89AB to the FMC_KEY0 register After the two write operations the LK bit in FMC_CTL0 register is ...

Page 46: ...isters Write the page absolute address 0x08XX XXXX into the FMC_ADDRx registers Send the page erase command to the FMC by setting the START bit in FMC_CTLx registers Wait until all the operations have finished by checking the value of the BUSY bit in FMC_STATx registers Read and verify the page by using a DBUS access if required When the operation is executed successfully the ENDF in FMC_STATx reg...

Page 47: ...ss should not only be written to FMC_ADRR1 but also to FMC_ADDR0 2 3 5 Mass erase The FMC provides a complete erase function which is used to initialize the main flash block contents This erase can affect only on bank0 by setting MER bit to 1 in the FMC_CTL0 register or only on bank1 by setting MER bit to 1 in the FMC_CTL1 register or on entire flash by setting MER bits to 1 in FMC_CTL0 register a...

Page 48: ...if the ENDIE bit in the FMC_CTLx registers is set Since all flash data will be modified to a value of 0xFFFF_FFFF the mass erase operation can be implemented using a program that runs in SRAM or by using the debugging tool that accesses the FMC registers directly For the GD32F20x_CL with flash size more than 512KB the mass erase procedure applied to bank1 is similar to the procedure applied to ban...

Page 49: ...ired When the operation is executed successfully the ENDF in FMC_STATx registers is set and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTLx registers is set Note that the word half word programming operation checks the address if it has been erased If the address has not been erased PGERR bit in the FMC_STATx registers will be set when programming the address except 0x0 Note...

Page 50: ...d flash memory accesses failed if the CPU enters the power saving modes 2 3 7 Option bytes Erase The FMC provides an erase function which is used to initialize the option bytes block in flash The following steps show the erase sequence Unlock the FMC_CTL0 register if necessary Check the BUSY bit in FMC_STAT0 register to confirm that no Flash memory operation is in progress BUSY equal to 0 Otherwis...

Page 51: ... the OBPG bit in FMC_CTL0 register A 32 bit word 16 bit half word write at desired address by DBUS Wait until all the operations have been finished by checking the value of the BUSY bit in FMC_STAT0 register Read and verify the Flash memory by using a DBUS access if required When the operation is executed successfully the ENDF in FMC_STAT0 register is set and an interrupt will be triggered by FMC ...

Page 52: ...ned data bit 7 to 0 0x1fff f805 DATA_N 7 0 DATA complement value bit 7 to 0 0x1fff f806 DATA 15 8 user defined data bit 15 to 8 0x1fff f807 DATA_N 15 8 DATA complement value bit 15 to 8 0x1fff f808 WP 7 0 Page Erase Program Protection bit 7 to 0 0 protection active 1 unprotected 0x1fff f809 WP_N 7 0 WP complement value bit 7 to 0 0x1fff f80a WP 15 8 Page Erase Program Protection bit 15 to 8 0x1fff...

Page 53: ...tion performed The main flash and option bytes block are accessible by all operations Under protection when setting SPC byte and its complement value to any value except 0x5AA5 the security protection is performed Note that a power reset should be followed instead of a system reset if the SPC modification is performed while the debug module is still connected to JTAG SWD device Under the security ...

Page 54: ...d 011 111 reserved 2 4 2 Unlock key register 0 FMC_KEY0 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 15 0 w Bits Fields Descriptions 31 0 KEY 31 0 FMC_CTL0 unlock key These bits are only be written by software Write KEY 31 0 with keys to unlock FMC_CT...

Page 55: ...BUSY rc_w1 rc_w1 rc_w1 r Bits Fields Descriptions 31 6 Reserved Must be kept at reset value 5 ENDF End of operation flag bit When the operation executed successfully this bit is set by hardware The software can clear it by writing 1 4 WPERR Erase Program protection error flag bit When erase program on protected pages this bit is set by hardware The software can clear it by writing 1 3 Reserved Mus...

Page 56: ...alue 10 ERRIE Error interrupt enable bit This bit is set or cleared by software 0 no interrupt generated by hardware 1 error interrupt enable 9 OBWEN Option byte erase program enable bit This bit is set by hardware when right sequence written to FMC_OBKEY register This bit can be cleared by software 8 Reserved Must be kept at reset value 7 LK FMC_CTL0 lock bit This bit is cleared by hardware when ...

Page 57: ...am command for bank0 Note This register should be reset after the corresponding flash operation completed 2 4 6 Address register 0 FMC_ADDR0 Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR 15 0 W Bits Fields Descriptions 31 0 ADDR 31 0 Flash erase prog...

Page 58: ...t is set by hardware when the option bytes and its complement byte do not match then the option bytes is set to 0xFF 2 4 8 Erase Program Protection register FMC_WP Address offset 0x20 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WP 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WP 15 0 r Bits Fields Descriptions 31 0 WP 31 0...

Page 59: ...ds Descriptions 31 6 Reserved Must be kept at reset value 5 ENDF End of operation flag bit When the operation executed successfully this bit is set by hardware The software can clear it by writing 1 4 WPERR Erase Program protection error flag bit When erase program on protected pages this bit is set by hardware The software can clear it by writing 1 3 Reserved Must be kept at reset value 2 PGERR P...

Page 60: ...st be kept at reset value 10 ERRIE Error interrupt enable bit This bit is set or cleared by software 0 no interrupt generated by hardware 1 error interrupt enable 9 8 Reserved Must be kept at reset value 7 LK FMC_CTL1 lock bit This bit is cleared by hardware when right sequence written to FMC_KEY1 register This bit can be set by software 6 START Send erase command to FMC bit This bit is set by sof...

Page 61: ...6 ADDR 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR 15 0 W Bits Fields Descriptions 31 0 ADDR 31 0 Flash erase program command address bits These bits are configured by software ADDR bits are the address of flash erase program command 2 4 13 Wait state enable register FMC_WSEN Address offset 0xFC Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 ...

Page 62: ...FMC_PID Address offset 0x100 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PID 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PID 15 0 r Bits Fields Descriptions 31 0 PID 31 0 Product reserved ID code These bits are read only by software These bits are unchanged constant after power on These bits are one time program when the...

Page 63: ... is supplied directly by VDD An embedded LDO in the VDD VDDA domain is used to supply the 1 2V domain power A power switch is implemented for the Backup domain It can be powered from the VBAT voltage when the main VDD supply is shut down 3 2 Characteristics Three power domains VBAK domain VDD VDDA domain and 1 2V power domain Three power saving modes Sleep mode Deep sleep mode and Standby mode Int...

Page 64: ...wn VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source The power switch is controlled by the Power Down Reset circuit in the VDD VDDA domain If no external battery is used in the application it is recommended to connect VBAT pin externally to VDD pin with a 100nF external ceramic decoupling capacitor The Backup domain reset sources includes the Backu...

Page 65: ...5 should not exceed 2MHz when they are in output mode maximum load 30pF 3 3 2 VDD VDDA power domain VDD VDDA domain includes two parts VDD domain and VDDA domain VDD domain includes HXTAL High Speed Crystal oscillator LDO Voltage Regulator POR PDR Power On Down Reset FWDGT Free Watchdog Timer all pads except PC13 PC14 PC15 etc VDDA domain includes ADC DAC AD DA Converter IRC8M Internal 8MHz RC osc...

Page 66: ..._CS indicates if VDD VDDA is higher or lower than the LVD threshold This event is internally connected to the EXTI line 16 and can generate an interrupt if it is enabled through the EXTI registers Figure 3 3 Waveform of the LVD threshold shows the relationship between the LVD threshold and the LVD output LVD interrupt signal depends on EXTI line 16 rising or falling edge configuration The followin...

Page 67: ...o enter the expected power saving mode the associated control bits must be configured Then once a WFI Wait for Interrupt or WFE Wait for Event instruction is executed the device will enter an expected power saving mode which will be discussed in the following section 3 3 4 Power saving modes After a system reset or a power reset the GD32F20x MCU operates at full function and all power domains are ...

Page 68: ...o enter Deep sleep mode smoothly all EXTI line pending status in the EXTI_PD register and RTC Alarm must be reset If not the program will skip the entry process of Deep sleep mode to continue to execute the following procedure Standby mode The Standby mode is based on the SLEEPDEEP mode of the Cortex M3 too In Standby mode the whole 1 2V domain is power off the LDO is shut down and all of IRC8M HX...

Page 69: ...D 1 WURST 1 Entry WFI or WFE WFI or WFE WFI or WFE Wakeup Any interrupt for WFI Any event or interrupt when SEVONPEND is 1 for WFE Any interrupt from EXTI lines for WFI Any event or interrupt when SEVONPEND is 1 from EXTI for WFE 1 NRST pin 2 WKUP pin 3 FWDGT reset 4 RTC Wakeup Latency None IRC8M wakeup time LDO wakeup time added if LDO is in low power mode Power on sequence ...

Page 70: ... 9 Reserved Must be kept at reset value 8 BKPWEN Backup Domain Write Enable 0 Disable write access to the registers in Backup domain 1 Enable write access to the registers in Backup domain After reset any write access to the registers in Backup domain is ignored This bit has to be set to enable write access to these registers 7 5 LVDT 2 0 Low Voltage Detector Threshold 000 2 2V 001 2 3V 010 2 4V 0...

Page 71: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WUPEN Reserved LVDF STBF WUF rw r r r Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 WUPEN WKUP Pin Enable 0 Disable WKUP pin function 1 Enable WKUP pin function If WUPEN is set before entering the power saving mode a rising edge on the WKUP pin wakes up the system from the power saving mode As the WKUP pin is active high the WKUP pin is...

Page 72: ...R PDR or by setting the STBRST bit in the PMU_CTL register 0 WUF Wakeup Flag 0 No wakeup event has been received 1 Wakeup event occurred from the WKUP pin or the RTC wakeup event including RTC Tamper event RTC alarm event RTC Time Stamp event or RTC Wakeup This bit is cleared only by a POR PDR or by setting the WURST bit in the PMU_CTL register ...

Page 73: ... the registers in Backup domain should be enabled by setting the BKPWEN bit in the PMU_CTL register 4 2 Characteristics 84 bytes Backup registers which can keep data under power saving mode If tamper event is detected Backup registers will be reset The active level of Tamper source PC13 and PI8 can be configured RTC Clock Calibration register provides RTC alarm and second output selection and sets...

Page 74: ... PI8 by setting corresponding TPEN1 bit in the BKP_TPCTL register To prevent the tamper event from losing the edge detection is logically ANDed with the TPEN1 bit the result is used as tamper detection signal So the tamper detection configuration should be set before enable TAMPER1 pin When the tamper event is detected the corresponding TEF1 bit in the BKP_TPCS register will be set Tamper event ca...

Page 75: ...n if the wake up action from Standby mode or system reset or power reset 4 4 2 RTC signal output control register BKP_OCTL Address offset 0x2C Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CALDIR CCOSEL Reserved ROSEL ASOEN COEN RCCV 6 0 rw rw rw rw rw rw Bits Fields Descriptions 15 CALDIR RTC clock calibration direction 0...

Page 76: ... reset only by a POR PDR 6 0 RCCV 6 0 RTC clock calibration value The value indicates how many clock pulses are ignored or added every 2 20 RTC clock pulses 4 4 3 Tamper pin control register0 BKP_TPCTL0 Address offset 0x30 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TPAL0 TPEN0 rw rw Bits Fields Descriptions 15 ...

Page 77: ...st be kept at reset value 9 TIF0 Tamper0 interrupt flag 0 No tamper0 interrupt occurred 1 A tamper0 interrupt occurred This bit is reset by writing 1 to the TIR0 bit or the TPIE0 bit being 0 8 TEF0 Tamper0 event flag 0 No tamper0 event occurred 1 A tamper0 event occurred This bit is reset by writing 1 to the TER0 bit 7 TPIE1 Tamper1 waveform detect interrupt enable 0 Disable the tamper1 interrupt ...

Page 78: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPM1 TPM2 Reserved TPAL1 TPEN1 Reserved w w rw rw Bits Fields Descriptions 15 TPM1 The first Waveform detection enable 0 No effect 1 Detect waveform of RTCCLK 64 need configure CCOSEL to 0 TPEN0 TPEN1 to 0 PC13 PI8 14 TPM2 The second Waveform detection enable 0 No effect 1 Detect waveform of RTCCLK 64 need configure CCOSEL to 0 TPEN0 TPEN1 to 0 PC14 PC15 13 10...

Page 79: ...GD32F20x User Manual 79 on the TAMPER1 pin resets all data of the BKP_DATAx register 7 0 Reserved Must be kept at reset value ...

Page 80: ...nal reset generator when exiting Standby mode The power reset sets all registers to their reset values except the Backup domain The Power reset which active signal is low it will be de asserted when the internal LDO voltage regulator is ready to provide 1 2V power The RESET service routine vector is fixed at address 0x0000_0004 in the memory map System Reset A system reset is generated by the foll...

Page 81: ... CCTL 5 2 1 Overview The clock control unit provides a series of frequency clock functions These include a Internal 8M RC oscillator IRC8M a High Speed crystal oscillator HXTAL a Low Speed Internal 40K RC oscillator IRC40K a Low Speed crystal oscillator LXTAL three Phase Lock Loop PLL PLL1 and PLL2 a HXTAL clock monitor clock prescalers clock multiplexers and clock gating circuitry The clocks of t...

Page 82: ... 1 2 3 15 16 PREDV1 8 9 10 14 16 20 PLL1 PLL1MF PLL2MF 8 9 10 14 16 20 PLL2 CK_PLL1 CK_PLL2 1 2 3 15 16 x2 I2S1 2SEL 0 1 CK_I2S to I2S1 2 1 2 20 0 1 CK_MACTX 0 1 CK_MACRX CK_FMC to FMC Ethernet PHY EXT1 to CK_OUT CK_MACRMII PREDV0SEL CKOUT0DIV 1 2 64 CK_OUT1 CK_PLL CK_HXTAL CK_IRC8M CK_SYS 2 0111 00xx NO CLK 0100 0101 0110 CKOUT1SEL 3 0 EXT1 2 1000 1001 1010 CK_PLL1 CK_PLL2 1011 CK_PLL2 CKOUT1DIV ...

Page 83: ...ister The Ethernet MAC is clocked by the external PHY If using the Ethernet module it must keep the AHB clock frequency at least 25 MHz The RTC is clocked by LXTAL clock or IRC40K clock or HXTAL clock divided by 128 which select by RTCSRC bit in Backup Domain Control Register RCU_BDCTL The FWDGT is clocked by IRC40K clock which is forced on when FWDGT started 5 2 2 Characteristics 3 to 25 MHz High...

Page 84: ... is powered up The IRC8M oscillator provides a lower cost type clock source as no external components are required The IRC8M RC oscillator can be switched on or off using the IRC8MEN bit in the control register RCU_CTL The IRC8MSTB flag in the Control register RCU_CTL is used to indicate if the internal RC oscillator is stable The start up time of the IRC8M oscillator is shorter than the HXTAL cry...

Page 85: ...gured by PLL2MF 3 0 PLL1MF 3 0 and PREDV1 3 0 bits in the configuration register 1 RCU_CFG1 Low speed crystal oscillator LXTAL The low speed external crystal or ceramic resonator oscillator which has a frequency of 32 768 Hz produces a low power but highly accurate clock source for the Real Time Clock circuit The LXTAL oscillator can be switched on or off by setting the LXTALEN bit in the backup d...

Page 86: ...HXTAL clock stuck interrupt flag CKMIF in the Interrupt register RCU_INT will be set and the HXTAL failure event will be generated This failure interrupt is connected to the Non Maskable Interrupt NMI of the Cortex M3 If the HXTAL is selected as the clock source of CK_SYS PLL and CK_RTC the HXTAL failure will force the CK_SYS source to IRC8M the PLL will be disabled automatically If the HXTAL is s...

Page 87: ...1SEL Clock Source 00xx No Clock 0100 CK_SYS 0101 CK_IRC8M 0110 CK_HXTAL 0111 CK_PLL 2 1000 CK_PLL1 1001 CK_PLL2 2 1010 EXT1 1011 CK_PLL2 The CKOUT1 frequency can be reduced by a configurable binary divider controlled by the CKOUT1DIV 5 0 bits in the configuration register 2 RCU_CFG2 Voltage control The 1 2V domain voltage in Deep sleep mode can be controlled by DSLPVS 2 0 bit in the Deep sleep mod...

Page 88: ...st be kept at reset value 29 PLL2STB PLL2 Clock Stabilization Flag Set by hardware to indicate if the PLL2 output clock is stable and ready for use 0 PLL2 is not stable 1 PLL2 is stable 28 PLL2EN PLL2 enable Set and reset by software Reset by hardware when entering Deep sleep or Standby mode 0 PLL2 is switched off 1 PLL2 is switched on 27 PLL1STB PLL1 Clock Stabilization Flag Set by hardware to in...

Page 89: ...peed crystal oscillator HXTAL clock bypass mode enable The HXTALBPS bit can be written only if the HXTALEN is 0 0 Disable the HXTAL Bypass mode 1 Enable the HXTAL Bypass mode in which the HXTAL output clock is equal to the input clock 17 HXTALSTB High speed crystal oscillator HXTAL clock stabilization flag Set by hardware to indicate if the HXTAL oscillator is stable and ready for use 0 HXTAL osci...

Page 90: ...alue 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PLLMF 4 ADCPSC 2 CKOUT0SEL 3 0 USBFSPSC 1 0 PLLMF 3 0 PREDV0 _LSB PLLSEL rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCPSC 1 0 APB2PSC 2 0 APB1PSC 2 0 AHBPSC 3 0 SCSS 1 0 SCS 1 0 rw rw rw rw r rw Bits Fields Descriptions 31 30 Reserv...

Page 91: ...eed 120 MHz 00000 PLL source clock x 2 00001 PLL source clock x 3 00010 PLL source clock x 4 00011 PLL source clock x 5 00100 PLL source clock x 6 00101 PLL source clock x 7 00110 PLL source clock x 8 00111 PLL source clock x 9 01000 PLL source clock x 10 01001 PLL source clock x 11 01010 PLL source clock x 12 01011 PLL source clock x 13 01100 PLL source clock x 14 01101 PLL source clock x 6 5 011...

Page 92: ... written by software to define the ADC prescaler factor Set and cleared by software 000 CK_APB2 2 selected 001 CK_APB2 4 selected 010 CK_APB2 6 selected 011 CK_APB2 8 selected 100 CK_APB2 2 selected 101 CK_APB2 12 selected 110 CK_APB2 8 selected 111 CK_APB2 16 selected 13 11 APB2PSC 2 0 APB2 prescaler selection Set and reset by software to control the APB2 clock division ratio 0xx CK_AHB selected ...

Page 93: ...p sleep and Standby mode or HXTAL failure is detected by HXTAL clock monitor when HXTAL is selected directly or indirectly as the clock source of CK_SYS 00 select CK_IRC8M as the CK_SYS source 01 select CK_HXTAL as the CK_SYS source 10 select CK_PLL as the CK_SYS source 11 reserved 5 3 3 Interrupt register RCU_INT Address offset 0x08 Reset value 0x0000 0000 This register can be accessed by byte 8 ...

Page 94: ...0 Not reset HXTALSTBIF flag 1 Reset HXTALSTBIF flag 18 IRC8MSTBIC IRC8M Stabilization Interrupt Clear Write 1 by software to reset the IRC8MSTBIF flag 0 Not reset IRC8MSTBIF flag 1 Reset IRC8MSTBIF flag 17 LXTALSTBIC LXTAL Stabilization Interrupt Clear Write 1 by software to reset the LXTALSTBIF flag 0 Not reset LXTALSTBIF flag 1 Reset LXTALSTBIF flag 16 IRC40KSTBIC IRC40K Stabilization Interrupt ...

Page 95: ... interrupt 1 Enable the LXTAL stabilization interrupt 8 IRC40KSTBIE IRC40K Stabilization interrupt enable IRC40K stabilization interrupt enable disable control 0 Disable the IRC40K stabilization interrupt 1 Enable the IRC40K stabilization interrupt 7 CKMIF HXTAL Clock Stuck Interrupt Flag Set by hardware when the HXTAL clock is stuck Reset when setting the CKMIC bit by software 0 Clock operating n...

Page 96: ...crystal oscillator clock is stable and the LXTALSTBIE bit is set Reset when setting the LXTALSTBIC bit by software 0 No LXTAL stabilization interrupt generated 1 LXTAL stabilization interrupt generated 0 IRC40KSTBIF IRC40K stabilization interrupt flag Set by hardware when the Internal 40kHz RC oscillator clock is stable and the IRC40KSTBIE bit is set Reset when setting the IRC40KSTBIC bit by softw...

Page 97: ...6 Reserved Must be kept at reset value 15 ADC2RST ADC2 reset This bit is set and reset by software 0 No reset 1 Reset the ADC2 14 USART0RST USART0 Reset This bit is set and reset by software 0 No reset 1 Reset the USART0 13 TIMER7RST Timer 7 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER7 12 SPI0RST SPI0 reset This bit is set and reset by software 0 No reset 1 Reset the S...

Page 98: ...eset 1 Reset the GPIO port E 5 PDRST GPIO port D reset This bit is set and reset by software 0 No reset 1 Reset the GPIO port D 4 PCRST GPIO port C reset This bit is set and reset by software 0 No reset 1 Reset the GPIO port C 3 PBRST GPIO port B reset This bit is set and reset by software 0 No reset 1 Reset the GPIO port B 2 PARST GPIO port A reset This bit is set and reset by software 0 No reset...

Page 99: ...T TIMER4 RST TIMER3 RST TIMER2 RST TIMER1 RST rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 DACRST DAC reset This bit is set and reset by software 0 No reset 1 Reset DAC unit 28 PMURST Power control reset This bit is set and reset by software 0 No reset 1 Reset power control unit 27 BKPIRST Backup interface reset This bit is set and rese...

Page 100: ... and reset by software 0 No reset 1 Reset the USART2 17 USART1RST USART1 reset This bit is set and reset by software 0 No reset 1 Reset the USART1 16 Reserved Must be kept at reset value 15 SPI2RST SPI2 reset This bit is set and reset by software 0 No reset 1 Reset the SPI2 14 SPI1RST SPI1 reset This bit is set and reset by software 0 No reset 1 Reset the SPI1 13 12 Reserved Must be kept at reset ...

Page 101: ...Reset the TIMER6 4 TIMER5RST TIMER5 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER5 3 TIMER4RST TIMER4 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER4 2 TIMER3RST TIMER3 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER3 1 TIMER2RST TIMER2 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER2 0 TIMER1RST...

Page 102: ...ed Ethernet RX clock 1 Enabled Ethernet RX clock 15 ENETTXEN Ethernet TX clock enable This bit is set and reset by software 0 Disabled Ethernet TX clock 1 Enabled Ethernet TX clock 14 ENETEN Ethernet clock enable This bit is set and reset by software 0 Disabled Ethernet clock 1 Enabled Ethernet clock 13 Reserved Must be kept at reset value 12 USBFSEN USBFS clock enable This bit is set and reset by...

Page 103: ...enable disable SRAM interface clock during Sleep mode 0 Disabled SRAM interface clock during Sleep mode 1 Enabled SRAM interface clock during Sleep mode 1 DMA1EN DMA1 clock enable This bit is set and reset by software 0 Disabled DMA1 clock 1 Enabled DMA1 clock 0 DMA0EN DMA0 clock enable This bit is set and reset by software 0 Disabled DMA0 clock 1 Enabled DMA0 clock 5 3 7 APB2 enable register RCU_...

Page 104: ...R8 clock 1 Enabled TIMER8 clock 18 16 Reserved Must be kept at reset value 15 ADC2EN ADC2 clock enable This bit is set and reset by software 0 Disabled ADC2 clock 1 Enabled ADC2 clock 14 USART0EN USART0 clock enable This bit is set and reset by software 0 Disabled USART0 clock 1 Enabled USART0 clock 13 TIMER7EN TIMER7 clock enable This bit is set and reset by software 0 Disabled TIMER7 clock 1 Ena...

Page 105: ...software 0 Disabled GPIO port E clock 1 Enabled GPIO port E clock 5 PDEN GPIO port D clock enable This bit is set and reset by software 0 Disabled GPIO port D clock 1 Enabled GPIO port D clock 4 PCEN GPIO port C clock enable This bit is set and reset by software 0 Disabled GPIO port C clock 1 Enabled GPIO port C clock 3 PBEN GPIO port B clock enable This bit is set and reset by software 0 Disabled...

Page 106: ...4 EN TIMER3 EN TIMER2 EN TIMER1 EN rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 DACEN DAC clock enable This bit is set and reset by software 0 Disabled DAC clock 1 Enabled DAC clock 28 PMUEN PMU clock enable This bit is set and reset by software 0 Disabled PMU clock 1 Enabled PMU clock 27 BKPIEN Backup interface clock enable This bit is...

Page 107: ...UART3 clock 18 USART2EN USART2 clock enable This bit is set and reset by software 0 Disabled USART2 clock 1 Enabled USART2 clock 17 USART1EN USART1 clock enable This bit is set and reset by software 0 Disabled USART1 clock 1 Enabled USART1 clock 16 Reserved Must be kept at reset value 15 SPI2EN SPI2 clock enable This bit is set and reset by software 0 Disabled SPI2 clock 1 Enabled SPI2 clock 14 SP...

Page 108: ...is bit is set and reset by software 0 Disabled TIMER6 clock 1 Enabled TIMER6 clock 4 TIMER5EN TIMER5 clock enable This bit is set and reset by software 0 Disabled TIMER5 clock 1 Enabled TIMER5 clock 3 TIMER4EN TIMER4 clock enable This bit is set and reset by software 0 Disabled TIMER4 clock 1 Enabled TIMER4 clock 2 TIMER3EN TIMER3 clock enable This bit is set and reset by software 0 Disabled TIMER...

Page 109: ...TB LXTALEN rw rw rw rw r rw Bits Fields Descriptions 31 17 Reserved Must be kept at reset value 16 BKPRST Backup domain reset This bit is set and reset by software 0 No reset 1 Resets Backup domain 15 RTCEN RTC clock enable This bit is set and reset by software 0 Disabled RTC clock 1 Enabled RTC clock 14 10 Reserved Must be kept at reset value 9 8 RTCSRC 1 0 RTC clock entry selection Set and reset...

Page 110: ...sable LXTAL 1 Enable LXTAL 5 3 10 Reset source clock register RCU_RSTSCK Address offset 0x24 Reset value 0x0C00 0000 ALL reset flags reset by power Reset only RSTFC IRC40KEN reset by system reset This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LP RSTF WWDGT RSTF FWDGT RSTF SW RSTF POR RSTF EP RSTF Reserved RSTFC Reserved ...

Page 111: ...TF Power reset flag Set by hardware when a Power reset generated Reset by writing 1 to the RSTFC bit 0 No Power reset generated 1 Power reset generated 26 EPRSTF External PIN reset flag Set by hardware when an External PIN reset generated Reset by writing 1 to the RSTFC bit 0 No External PIN reset generated 1 External PIN reset generated 25 Reserved Must be kept at reset value 24 RSTFC Reset flag ...

Page 112: ...reset This bit is set and reset by software 0 No reset 1 Reset the ENET 13 Reserved Must be kept at reset value 12 USBFSRST USBFS reset This bit is set and reset by software 0 No reset 1 Reset the USBFS 11 0 Reserved Must be kept at reset value 5 3 12 Configuration register 1 RCU_CFG1 Address offset 0x2C Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word ...

Page 113: ...clock 15 12 PLL2MF 3 0 PLL2 multiply factor These bits are written by software to define the PLL2 multiplication factor 00xx reserve 010x reserve 0110 PLL2 source clock x 8 0111 PLL2 source clock x 9 1000 PLL2 source clock x 10 1001 PLL2 source clock x 11 1010 PLL2 source clock x 12 1011 PLL2 source clock x 13 1100 PLL2 source clock x 14 1101 PLL2 source clock x 15 1110 PLL2 source clock x 16 1111...

Page 114: ... source clock divided by 16 3 0 PREDV0 PREDV0 division factor This bit is set and reset by software These bits can be written when PLL is disable Note The bit 0 of PREDV0 is same as bit 17 of RCU_CFG0 so modifying Bit 17 of RCU_CFG0 aslo modifies bit 0 of RCU_CFG1 0000 PREDV0 input source clock not divided 0001 PREDV0 input source clock divided by 2 0010 PREDV0 input source clock divided by 3 0011...

Page 115: ...leep mode 010 The core voltage is 1 0V in Deep sleep mode 011 The core voltage is 0 9V in Deep sleep mode 1xx Reserved 5 3 14 AHB2 enable register RCU_AHB2EN Address offset 0x60 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRNGEN HAUEN CAUE...

Page 116: ... bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PIEN PHEN Reserved TLIEN Reserved USART5EN Reserved rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Fields Descriptions 31 PIEN GPIO port I clock enable This bit is set and reset by software 0 Disabled GPIO port I clock 1 Enabled GPIO port I clock 30 PHEN GPIO port H clock enable This bit is set and reset by softw...

Page 117: ...UART6 EN Reserved I2C2EN Reserved rw rw rw 5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Fields Descriptions 31 UART7EN UART7 clock enable This bit is set and reset by software 0 Disabled UART7 clock 1 Enabled UART7 clock 30 UART6EN UART6 clock enable This bit is set and reset by software 0 Disabled UART6 clock 1 Enabled UART6 clock 29 24 Reserved Must be kept at reset value 23 I2C2EN I2C2 cl...

Page 118: ... HAU reset This bit is set and reset by software 0 No reset 1 Reset the HAU 4 CAURST CAU reset This bit is set and reset by software 0 No reset 1 Reset the CAU 3 1 Reserved Must be kept at reset value 0 DCIRST DCI reset This bit is set and reset by software 0 No reset 1 Reset the DCI 5 3 18 APB2 additional reset register RCU_ADDAPB2RST Address offset 0x74 Reset value 0x0000 0000 This register can ...

Page 119: ...ed Must be kept at reset value 24 USART5RST USART5 reset This bit is set and reset by software 0 No reset 1 Reset the USART5 23 0 Reserved Must be kept at reset value 5 3 19 APB1 additional reset register RCU_ADDAPB1RST Address offset 0x78 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UART7 RST U...

Page 120: ...19 18 17 16 Reserved CKOUT1SEL 3 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CKOUT1DIV 5 0 Reserved CKOUT0DIV 5 0 rw rw Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 16 CKOUT1SEL 3 0 CKOUT1 clock source selection Set and reset by software 00xx No clock selected 0100 System clock selected 0101 High Speed 8M Internal Oscillator clock IRC8M selected 0110 External High...

Page 121: ...ivided by 64 5 3 21 PLLT control register RCU_PLLTCTL Address offset 0x90 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PLLTSTB PLLTEN Reserved r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 PLLTSTB PLLT Clock St...

Page 122: ...TSTBIF flag 21 15 Reserved Must be kept at reset value 14 PLLTSTBIE PLLT Stabilization Interrupt Enable Set and reset by software to enable disable the PLLT stabilization interrupt 0 Disable the PLLT stabilization interrupt 1 Enable the PLLT stabilization interrupt 13 7 Reserved Must be kept at reset value 6 PLLTSTBIF PLLT stabilization interrupt flag Set by hardware when the PLLT is stable and th...

Page 123: ...iguration 010 PLLTRPSC 2 111 PLLTRPSC 7 27 18 Reserved Must be kept at reset value 17 16 TLIPSC 1 0 TLI prescaler selection These bits are set and cleared by software to control the frequency of CK_TLI They should be written only if PLLT is disabled CK_TLI frequency f PLLTR TLIPSC with 2 TLIPSC 16 00 TLIPSC 2 01 TLIPSC 4 10 TLIPSC 8 11 TLIPSC 16 15 Reserved Must be kept at reset value 14 6 PLLTMF ...

Page 124: ...ly when PLLT is disabeled Note The software has to set these bits correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz It is recommended to select a frequency of 2 MHz to limit PLL jitter VCO input frequency PLLT input clock frequency PLLTPSC with 2 PLLTPSC 63 000000 PLLTPSC 0 wrong configuration 000001 PLLTPSC 1 wrong configuration 000010 PLLTPSC 2 000011 PLLTPSC 3 000100 PLLTP...

Page 125: ...eripheral interrupts 4 bits interrupt priority configuration 16 priority levels Efficient interrupt processing Support exception pre emption and tail chaining Wake up system from power saving mode Up to 20 independent edge detectors in EXTI Three trigger types rising falling and both edges Software interrupt or event trigger Trigger sources configurable 6 3 Interrupts function overview The ARM Cor...

Page 126: ...000_003C System tick timer The SysTick calibration value is 15000 and SysTick clock frequency is fixed to HCLK 0 125 So this will give a 1ms SysTick interrupt if HCLK is configured to 120MHz Table 6 2 Interrupt vector table Interrupt Number Vector Number Peripheral Interrupt Description Vector Address IRQ 0 16 WWDGT interrupt 0x0000_0040 IRQ 1 17 LVD from EXTI interrupt 0x0000_0044 IRQ 2 18 Tamper...

Page 127: ...upt 0x0000_00B0 IRQ 29 45 TIMER2 global interrupt 0x0000_00B4 IRQ 30 46 TIMER3 global interrupt 0x0000_00B8 IRQ 31 47 I2C0 event interrupt 0x0000_00BC IRQ 32 48 I2C0 error interrupt 0x0000_00C0 IRQ 33 49 I2C1 event interrupt 0x0000_00C4 IRQ 34 50 I2C1 error interrupt 0x0000_00C8 IRQ 35 51 SPI0 global interrupt 0x0000_00CC IRQ 36 52 SPI1 global interrupt 0x0000_00D0 IRQ 37 53 USART0 global interrup...

Page 128: ...akeup through EXTI line interrupt 0x0000_0138 IRQ 63 79 CAN1 TX interrupts 0x0000_013C IRQ 64 80 CAN1 RX0 interrupts 0x0000_0140 IRQ 65 81 CAN1 RX1 interrupt 0x0000_0144 IRQ 66 82 CAN1 EWMC interrupt 0x0000_0148 IRQ 67 83 USBFS global interrupt 0x0000_014C Reserved Reserved IRQ69 85 DMA1 Channel 5 global interrupt 0x0000_0154 IRQ70 86 DMA1 Channel 6 global interrupt 0x0000_0158 IRQ71 87 USART5 glo...

Page 129: ...es 16 external lines from GPIO pins and 4 lines from internal modules including LVD RTC Alarm USBFS Wakeup Ethernet Wakeup All GPIO pins can be selected as an EXTI trigger source by configuring AFIO_EXTISSx registers in GPIO module please refer to GPIO and AFIO section for detail EXTI can provide not only interrupts but also event signals to the processor The Cortex M3 processor fully implements t...

Page 130: ...7 PB7 PC7 PD7 PE7 PF7 PG7 PH7 PI7 External 8 PA8 PB8 PC8 PD8 PE8 PF8 PG8 PH8 PI8 External 9 PA9 PB9 PC90 PD9 PE9 PF9 PG9 PH9 PI9 External 10 PA10 PB10 PC10 PD10 PE10 PF10 PG10 PH10 PI10 External 11 PA11 PB11 PC11 PD11 PE11 PF11 PG11 PH11 PI11 External 12 PA12 PB12 PC12 PD12 PE12 PF12 PG12 PH12 External 13 PA13 PB13 PC13 PD13 PE13 PF13 PG13 PH13 External 14 PA14 PB14 PC14 PD14 PE14 PF14 PG14 PH14 E...

Page 131: ...ds Descriptions 31 20 Reserved Must be kept at reset value 19 0 INTENx Interrupt enablebit 0 Interrupt from Linex is disabled 1 Interrupt from Linex is enabled 6 6 2 Event enable register EXTI_EVEN Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved EVEN19 EVEN18 EVEN17 EVEN16 rw rw rw rw 15 14 13 12 1...

Page 132: ...d 1 Rising edge of Linex is valid as an interrupt event request 6 6 4 Falling edge trigger enable register EXTI_FTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FTEN19 FTEN18 FTEN17 FTEN16 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTEN15 FTEN14 FTEN13 FTEN12 FTEN11 FTEN10 FTEN9 FTEN8 FT...

Page 133: ... software interrupt event request 1 Activate the EXTIx software interrupt event request 6 6 6 Pending register EXTI_PD Address offset 0x14 Reset value undefined This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PD19 PD18 PD17 PD16 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD...

Page 134: ...iguring the corresponding registers regardless of the AF input or output pins Each of the GPIO pins can be configured by software as output push pull or open drain input peripheral alternate function or analog mode Each GPIO pin can be configured as pull up pull down or no pull up pull down All GPIOs are high current capable except for analog mode 7 2 Characteristics Input output direction control...

Page 135: ...d up to 50MHz 0 or 1 Open drain 01 0 or 1 Alternate Function Output AFIO Push pull 10 don t care Open drain 11 don t care Figure 7 1 The basic structure of a standard I O and five volt tolerant I O Port shows the basic structure of an I O port bit Figure 7 1 The basic structure of a standard I O and five volt tolerant I O Port Vss Vss Output Control Vdd Vdd_FT 1 Vdd_FT Port output control register...

Page 136: ...rt output control register GPIOx_OCTL is output on the I O pin There is no need to read then write when programming the GPIOx_OCTL at bit level user can modify only one or several bits in a single atomic APB2 write access by programming 1 to the bit operate register GPIOx_BOP or for clearing only GPIOx_BC The other bits will not be affected 7 3 2 External interrupt event lines All ports have exter...

Page 137: ...n Drain Mode The pad output low level when a 0 in the output control register while the pad leaves Hi Z when a 1 in the output control register Push Pull Mode The pad output low level when a 0 in the output control register while the pad output high level when a 1 in the output control register A read access to the port output control register gets the last written value A read access to the port ...

Page 138: ... for five volt tolerant I Os and is different from Vdd 7 3 7 Alternate function AF configuration To suit for different device packages the GPIO supports some alternate functions mapped to some other pins by software When be configured as alternate function The output buffer is enabled in Open Drain or Push Pull configuration The output buffer is driven by the peripheral The schmitt trigger input i...

Page 139: ...r 0b01 for GPIO open drain output Alternate function Each IO pin can be used for AF input function by configuring MDy bits to 0b00 in GPIOx_CTL0 GPIOx_CTL1 registers And set output function by configuring MDy bits to 0b01 0b10 or 0b11 and configuring CTLy bits of corresponding port in GPIOx_CTL0 GPIOx_CTL1 register to 0b10 for AF push pull output or 0b11 for AF open drain output 7 3 9 GPIO locking...

Page 140: ...the relevant EXTI Source Selection Register AFIO_EXTISSx to trigger an interrupt or event 7 4 2 Main features APB slave interface for register access EXTI source selection Each pin has up to four alternative functions for configuration 7 4 3 JTAG SWD alternate function remapping The debug interface signals are mapped on the GPIO ports as shown in table below Table 7 2 Debug interface signals Alter...

Page 141: ...l trigger inserted conversion is connected to TIMER7_CH3 Table 7 5 ADC0 external trigger regular conversion AF remapping Alternate function ADC0_ETRGREG_REMAP 0 ADC0_ETRGREG_REMAP 1 ADC0 external trigger regular conversion ADC0 external trigger regular conversion is connected to EXTI11 ADC0 external trigger regular conversion is connected to TIMER7_TRGO Table 7 6 ADC1 external trigger inserted con...

Page 142: ...rtial remap TIMER1_REMAP 1 0 10 partial remap TIMER1_REMAP 1 0 11 full remap TIMER1_CH0 TIMER 1_ETI 1 PA0 PA15 PA0 PA15 TIMER1_CH1 PA1 PB3 PA1 PB3 TIMER1_CH2 PA2 PB10 TIMER1_CH3 PA3 PB11 1 TIMER1_CH0 and TIMER1_ETI share the same pin but cannot be used at the same time In the chip datasheet marked as TIMER1_CH0_ETI Table 7 10 TIMER2 alternate function remapping Alternate function TIMER2_REMAP 1 0 ...

Page 143: ... PI5 TIMER7_CH1 PC7 PI6 TIMER7_CH2 PC8 PI7 TIMER7_CH3 PC9 PI2 TIMER7_BKIN PA6 PI4 TIMER7_CH0_ON PA7 PA5 PH13 TIMER7_CH1_ON PB0 PB14 PH14 TIMER7_CH2_ON PB1 PB15 PH15 Table 7 14 TIMER8 alternate function remapping 1 Alternate function TIMER8_REMAP 0 TIMER8_REMAP 1 TIMER8_CH0 PA2 PE5 TIMER8_CH1 PA3 PE6 1 Refer to the AF remap and debug I O configuration register 1 AFIO_ PCF1 Table 7 15 TIMER9 alterna...

Page 144: ...debug I O configuration register 1 AFIO_PCF1 7 4 6 USART AF remapping Refer to AFIO port configuration register 0 AFIO_PCF0 Table 7 20 USART0 alternate function remapping Alternate function USART0_REMAP 0 USART0_REMAP 1 USART0_TX PA9 PB6 USART0_RX PA10 PB7 Table 7 21 USART1 alternate function remapping Alternate function USART1_REMAP 0 USART1_REMAP 1 1 USART1_CTS PA0 PD3 USART1_RTS PA1 PD4 USART1_...

Page 145: ...ART6 alternate function remapping Alternate function UART6_REMAP 0 UART6_REMAP 1 UART6_TX PE8 PF7 UART6_RX PE7 PF6 7 4 7 I2C AF remapping Refer to AFIO port configuration register 0 AFIO_ PCF0 Table 7 26 I2C0 alternate function remapping Alternate function I2C0_REMAP 0 I2C0_REMAP 1 I2C0_SCL PB6 PB8 I2C0_SDA PB7 PB9 Table 7 27 I2C1 alternate function remapping Alternate function I2C1_REMAP 1 0 00 0...

Page 146: ...1_NSCK IO _REMAP 10 SPI1_NSCK IO _REMAP 11 SPI1_SCK _REMAP 1 SPI1_NSS I2S1_WS PB12 PI0 PB9 SPI1_SCK I2S1_CK PB13 PI1 PB10 PD3 SPI1_MISO PB14 PI2 PC2 SPI1_MOSI I2S2_SD PB15 PI3 PC3 I2S1_MCK PC6 Table 7 31 SPI2 I2S2 alternate function remapping 1 Alternate function SPI2_REMAP 0 SPI2_REMAP 1 SPI2_MOSI_REMAP 1 SPI2_NSS I2S2_WS PA15 PA4 SPI2_SCK I2S2_CK PB3 PC10 SPI2_MISO PB4 PC11 SPI2_MOSI I2S2_SD PB5...

Page 147: ...B13 PB6 7 4 10 Ethernet AF remapping Table 7 34 ENET alternate function remapping Alternate function ENET_R EMAP 0 ENET_R EMAP 1 ENET_RX_HI_REMAP ENET_CRSCOL_REMAP ENET_TXD01_REMAP ENET_RX_HI_REMAP ENET_CRSCOL_REMAP ENET_TXD01_REMAP ETH_MII_CRS PA0 PH2 ETH_MII_COL PA3 PH3 ETH_MII_RX_DV ETH_RMII_CRS_DV PA7 PD8 ETH_MII_RXD0 ETH_RMII_RXD0 PC4 PD9 ETH_MII_RXD1 ETH_RMII_RXD1 PC5 PD10 ETH_MII_RXD2 PB0 P...

Page 148: ...2 DCI_D4 PC11 PE4 PH14 DCI_D5 PB6 PD3 PI4 DCI_D6 PB8 PE5 PI6 DCI_D7 PB9 PE6 PI7 DCI_D8 PC10 PH6 PI1 DCI_D9 PC12 PH7 PI2 DCI_D10 PB5 PD6 PI3 DCI_D11 PD2 PF10 PH15 DCI_D12 PF11 PG6 DCI_D13 PG7 PG15 PI0 DCI_HSYNC PA4 PH8 DCI_VSYNC PB7 PG9 PI5 7 4 12 TLI AF remapping Table 7 36 TLI alternate function remapping Alternate function AFIO_PCF3 AFIO_PCF4 TLI_xx_Pn_ REMAP 1 1 TLI_xx_Pn_ REMAP 1 2 TLI_R0 PH2 ...

Page 149: ... 7 4 13 CLK pins AF remapping The LXTAL oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose I O PC14 and PC15 individually when the LXTAL oscillator is off The LXTAL has priority over the GPIOs function Note 1 But when the 1 8 V domain is powered off by entering standby mode or when the backup domain is supplied by VBAT VDD no more supplied the PC14 PC15 GPIO functionality is los...

Page 150: ...n PD01_REMAP 0 PD01_REMAP 1 PD0 PD0 OSC_IN PD1 PD1 OSC_OUT Table 7 39 OSC pins configuration 2 Alternate function PH01_REMAP 0 PH01_REMAP 1 1 PH0 OSC_IN PH1 OSC_OUT 1 Only for 176 pin packages PH0 PH1 default to OSC_IN OSC_OUT when PH01_REMAP 1 PH0 PH1 is general purpose IO port ...

Page 151: ... These bits are set and cleared by software refer to CTL0 1 0 description 29 28 MD7 1 0 Port 7 mode bits These bits are set and cleared by software refer to MD0 1 0 description 27 26 CTL6 1 0 Port 6 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 25 24 MD6 1 0 Port 6 mode bits These bits are set and cleared by software refer to MD0 1 0 description 23 22 ...

Page 152: ...n 7 6 CTL1 1 0 Port 1 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 5 4 MD1 1 0 Port 1 mode bits These bits are set and cleared by software refer to MD0 1 0 description 3 2 CTL0 1 0 Pin 0 configuration bits These bits are set and cleared by software Input mode MD 1 0 00 00 Analog mode 01 Floating input 10 Input with pull up pull down 11 Reserved Output...

Page 153: ... These bits are set and cleared by software refer to MD0 1 0 description 27 26 CTL14 1 0 Port 14 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 25 24 MD14 1 0 Port 14 mode bits These bits are set and cleared by software refer to MD0 1 0 description 23 22 CTL13 1 0 Port 13 configuration bits These bits are set and cleared by software refer to CTL0 1 0 de...

Page 154: ...s are set and cleared by software refer to MD0 1 0 description 3 2 CTL8 1 0 Port 8 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 1 0 MD8 1 0 Port 8 mode bits These bits are set and cleared by software refer to MD0 1 0 description 7 5 3 Port input status register GPIOx_ISTAT x A I Address offset 0x08 Reset value 0x0000 XXXX This register has to be acces...

Page 155: ...w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 OCTLy Port output control y 0 15 These bits are set and cleared by software 0 Pin output low 1 Pin output high 7 5 5 Port bit operate register GPIOx_BOP x A I Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CR15 CR14 CR13 CR12 CR11 C...

Page 156: ... 9 8 7 6 5 4 3 2 1 0 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 w w w w w w w w w w w w w w w w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CRy Port Clear bit y y 0 15 These bits are set and cleared by software 0 No action on the corresponding OCTLy bit 1 Clear the corresponding OCTLy bit to 0 7 5 7 Port configuration lock register GPIOx_LOCK...

Page 157: ...g bit port configuration is locked when LKK bit is 1 7 5 8 Event control register AFIO_EC Address offset 0x00 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EOE PORT 2 0 PIN 3 0 rw rw rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 EOE Event outpu...

Page 158: ...REMAP 1 0 TIMER3_ REMAP TIMER2_ REMAP 1 0 TIMER1_ REMAP 1 0 TIMER0_ REMAP 1 0 USART2_ REMAP 1 0 USART1_ REMAP USART0_ REMAP I2C0_ REMAP SPI0_ REMAP rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 Reserved Must be kept at reset value 30 PTP_PPS_REMAP Ethernet PTP PPS remapping This bit is set and cleared by software It enables the Ethernet MAC_PPS to be output on the PB5 pin 0 PPT_PPS ...

Page 159: ...C for connection with an MII PHY 1 Configure Ethernet MAC for connection with an RMII PHY 22 CAN1_REMAP CAN1 I O remapping This bit is set and cleared by software It controls the CAN1_TX and CAN1_RX pins 0 No remap CAN1_RX PB12 CAN_TX PB13 1 Remap CAN1_RX PB5 CAN_TX PB6 21 ENET_REMAP Ethernet MAC I O remapping This bit is set and cleared by software It controls the Ethernet MAC connections with PH...

Page 160: ...eared by software This bit controls the TIMER4_CH3 internal mapping When reset timer TIMER4_CH3 is connected to PA3 When set the IRC40K internal clock connected to TIMER4_CH3 input for calibration purpose 0 No remap 1 Remap 15 PD01_REMAP Port D0 Port D1 mapping on OSC_IN OSC_OUT This bit is set and cleared by software 0 Not remap 1 PD0 remapped on OSC_IN PD1 remapped on OSC_OUT 14 13 CAN0_REMAP 1 ...

Page 161: ...B15 01 Partial remap TIMER0_ETI PA12 TIMER0_CH0 PA8 TIMER0_CH1 PA9 TIMER0_CH2 PA10 TIMER0_CH3 PA11 TIMER0_BKIN PA6 TIMER0_CH0_ON PA7 TIMER0_CH1_ON PB0 TIMER0_CH2_ON PB1 10 Not used 11 Full remap TIMER0_ETI PE7 TIMER0_CH0 PE9 TIMER0_CH1 PE11 TIMER0_CH2 PE13 TIMER0_CH3 PE14 TIMER0_BKIN PE15 TIMER0_CH0_ON PE8 TIMER0_CH1_ON PE10 TIMER0_CH2_ON PE12 5 4 USART2_REMAP 1 0 USART2 remapping These bits are s...

Page 162: ...K PB3 SPI0_MISO PB4 SPI0_MOSI PB5 SPI0_IO2 PB6 SPI0_IO3 PB7 7 5 10 EXTI sources selection register 0 AFIO_EXTISS0 Address offset 0x08 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI3_SS 3 0 EXTI2_SS 3 0 EXTI1_SS 3 0 EXTI0_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Rese...

Page 163: ... PG1 pin 0111 PH1 pin 1000 PI1 pin Other configurations are reserved 3 0 EXTI0_SS 3 0 EXTI 0 sources selection 0000 PA0 pin 0001 PB0 pin 0010 PC0 pin 0011 PD0 pin 0100 PE0 pin 0101 PF0 pin 0110 PG0 pin 0111 PH0 pin 1000 PI0 pin Other configurations are reserved 7 5 11 EXTI sources selection register 1 AFIO_EXTISS1 Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word...

Page 164: ... PI7 pin Other configurations are reserved 11 8 EXTI6_SS 3 0 EXTI 6 sources selection 0000 PA6 pin 0001 PB6 pin 0010 PC6 pin 0011 PD6 pin 0100 PE6 pin 0101 PF6 pin 0110 PG6 pin 0111 PH6 pin 1000 PI6 pin Other configurations are reserved 7 4 EXTI5_SS 3 0 EXTI 5 sources selection 0000 PA5 pin 0001 PB5 pin 0010 PC5 pin 0011 PD5 pin 0100 PE5 pin 0101 PF5 pin 0110 PG5 pin 0111 PH5 pin 1000 PI5 pin Othe...

Page 165: ...ved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11_SS 3 0 EXTI10_SS 3 0 EXTI9_SS 3 0 EXTI8_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI11_SS 3 0 EXTI 11 sources selection 0000 PA11 pin 0001 PB11 pin 0010 PC11 pin 0011 PD11 pin 0100 PE11 pin 0101 PF11 pin 0110 PG11 pin 0111 PH11 pin 1000 PI11 pin Other configurations are reserved 11 8 EXTI10_SS 3 0...

Page 166: ...0011 PD8 pin 0100 PE8 pin 0101 PF8 pin 0110 PG8 pin 0111 PH8 pin 1000 PI8 pin Other configurations are reserved 7 5 13 EXTI sources selection register 3 AFIO_EXTISS3 Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI15_SS 3 0 EXTI14_SS 3 0 EXTI13_SS 3 0 EXTI1...

Page 167: ...SS 3 0 EXTI 13 sources selection 0000 PA13 pin 0001 PB13 pin 0010 PC13 pin 0011 PD13 pin 0100 PE13 pin 0101 PF13 pin 0110 PG13 pin Other configurations are reserved 3 0 EXTI12_SS 3 0 EXTI 12 sources selection 0000 PA12 pin 0001 PB12 pin 0010 PC12 pin 0011 PD12 pin 0100 PE12 pin 0101 PF12 pin 0110 PG12 pin Other configurations are reserved 7 5 14 AFIO port configuration register 1 AFIO_PCF1 Address...

Page 168: ...n onto the GPIO ports 0 No remap PA7 1 Remap PF9 8 TIMER12_REMAP TIMER12 remapping This bit is set and cleared by software it controls the mapping of the TIMER12_CH0 alternate function onto the GPIO ports 0 No remap PA6 1 Remap PF8 7 TIMER10_REMAP TIMER10 remapping This bit is set and cleared by software it controls the mapping of the TIMER10_CH0 alternate function onto the GPIO ports 0 No remap P...

Page 169: ...I_D0_ REMAP 1 0 DCI_VSYNC_ REMAP 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 PH01_ REMAP PH0 PH1 remapping This bit is set and cleared by software 0 No remap No PH0 PH1 use as OSC_IN OSC_OUT 1 PH0 PH1 remapped to OSC_IN OSC_OUT when 176 pins 30 Reserved Must be kept at reset value 29 DCI_HSYNC_ REMAP DCI_HSYNC remapping This bit is set and cleared by software 0 No remap PA4 1 DCI_HSYNC...

Page 170: ... set and cleared by software 00 No remap PC10 01 DCI_D8 remapped to PH6 10 Reserved 11 DCI_D8 remapped to PI1 17 16 DCI_D7_ REMAP 1 0 DCI_D7 remapping This bit is set and cleared by software 00 No remap PB9 01 DCI_D7 remapped to PE6 10 Reserved 11 DCI_D7 remapped to PI7 15 14 DCI_D6_ REMAP 1 0 DCI_D6 remapping This bit is set and cleared by software 00 No remap PB8 01 DCI_D6 remapped to PE5 10 Res...

Page 171: ...ped to PH11 5 4 DCI_D1_ REMAP 1 0 DCI_D1 remapping This bit is set and cleared by software 00 No remap PA10 01 DCI_D1 remapped to PC7 10 Reserved 11 DCI_D1 remapped to PH10 3 2 DCI_D0_ REMAP 1 0 DCI_D0 remapping This bit is set and cleared by software 00 No remap PA9 01 DCI_D0 remapped to PC6 10 Reserved 11 DCI_D0 remapped to PH9 1 0 DCI_VSYNC_ REMAP 1 0 DCI_VSYNC remapping This bit is set and cle...

Page 172: ... Fields Descriptions 31 TLI_B3_PG11 _REMAP TLI_B3_PG11 remapping This bit is set and cleared by software 0 TLI_B3 not remapped to PG11 1 TLI_B3 remapped to PG11 30 TLI_B2_PG10 _REMAP TLI_B2_PG10 remapping This bit is set and cleared by software 0 TLI_B2 not remapped to PG10 1 TLI_B2 remapped to PG10 29 TLI_G3_PG10 _REMAP TLI_G3_PG10 remapping This bit is set and cleared by software 0 TLI_G3 not re...

Page 173: ...pping This bit is set and cleared by software 0 TLI_ G1 not remapped to PE6 1 TLI_ G1 remapped to PE6 19 TLI_G0_PE5 _REMAP TLI_G0_PE5 remapping This bit is set and cleared by software 0 TLI_ G0 not remapped to PE5 1 TLI_ G0 remapped to PE5 18 TLI_B0_PE4 _REMAP TLI_B0_PE4 remapping This bit is set and cleared by software 0 TLI_ B0 not remapped to PE4 1 TLI_ B0 remapped to PE4 17 TLI_B3_PD10 _REMAP ...

Page 174: ... TLI_G4_PB10 _REMAP TLI_G4_PB10 remapping This bit is set and cleared by software 0 TLI_ G4 not remapped to PB10 1 TLI_ G4 remapped to PB10 9 TLI_B7_PB9 _REMAP TLI_B7_PB9 remapping This bit is set and cleared by software 0 TLI_ B7 not remapped to PB9 1 TLI_ B7 remapped to PB9 8 TLI_B6_PB8 _REMAP TLI_B6_PB8 remapping This bit is set and cleared by software 0 TLI_ B6 not remapped to PB8 1 TLI_ B6 re...

Page 175: ...software 0 TLI_ B5 not remapped to PA3 1 TLI_ B5 remapped to PA3 7 5 17 AFIO port configuration register 4 AFIO_PCF4 Address offset 0x44 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SPI2_ MOSI_ REMAP SPI1_ SCK_ REMAP TLI_R1_P I3_ REMAP TLI_R0_P H4_ REMAP TLI_HSY NC_PI10 _REMAP TLI_VSY NC_PI9_ REMAP TLI_B7_P I7_ REM...

Page 176: ...apped to PH4 20 TLI_HSYNC_PI10 _REMAP TLI_ HSYNC_PI10 remapping This bit is set and cleared by software 0 TLI_ HSYNC not remapped to PI10 1 TLI_ HSYNC remapped to PI10 19 TLI_VSYNC_PI9 _REMAP TLI_VSYNC_PI9 remapping This bit is set and cleared by software 0 TLI_ VSYNC not remapped to PI9 1 TLI_ VSYNC remapped to PI9 18 TLI_B7_PI7 _REMAP TLI_B7_PI7 remapping This bit is set and cleared by software ...

Page 177: ...4 not remapped to PH15 1 TLI_ G4 remapped to PH15 10 TLI_G3_PH14 _REMAP TLI_G3_PH14 remapping This bit is set and cleared by software 0 TLI_ G3 not remapped to PH14 1 TLI_ G3 remapped to PH14 9 TLI_G2_PH13 _REMAP TLI_G2_PH13 remapping This bit is set and cleared by software 0 TLI_ G2 not remapped to PH13 1 TLI_ G2 remapped to PH13 8 TLI_R6_PH12 _REMAP TLI_R6_PH12 remapping This bit is set and clea...

Page 178: ...remapping This bit is set and cleared by software 0 TLI_ B4 not remapped to PG12 1 TLI_ B4 remapped to PG12 7 5 18 AFIO port configuration register 5 AFIO_PCF5 Address offset 0x48 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXMC_S DNE1_ REMAP EXMC_S DNE0_ REMAP EXMC_S DCKE1_ REMAP EXMC_S DCKE0_ REMAP EXMC_S DNWE_ REMAP USA...

Page 179: ...KE0 remapped to PC3 27 EXMC_SDNWE_RE MAP EXMC_SDNWE remapping This bit is set and cleared by software 0 No remap PH5 1 EXMC_SDNWE remapped to PC0 26 USART5_RX_REMA P USART5_RX remapping This bit is set and cleared by software 0 No remap PC7 1 USART5_RX remapped to PG9 25 USART5_TX_REMA P USART5_TX remapping This bit is set and cleared by software 0 No remap PC6 1 USART5_TX remapped to PG14 24 USAR...

Page 180: ...nd cleared by software 0 No remap ETH_TX_EN ETH_TXD0 ETH_TXD1 mapped on PB11 PB12 PB13 1 ETH_TX_EN ETH_TXD0 ETH_TXD1 remapped to PG11 PG13 PG14 17 PPS_HI_REMAP ETH_ PPS_OUT remapping This bit is set and cleared by software 0 ETH_ PPS_OUT not remapped to PG8 1 ETH_ PPS_OUT remapped to PG8 16 ENET _TXD3_REMAP ETH_TXD3 remapping This bit is set and cleared by software 0 No remap ETH_TXD3 mapped on PB...

Page 181: ... ETI TIMER7_BKIN remapping This bit is set and cleared by software 0 No remap TIMER7_CH0 TIMER7_CH1 TIMER7_CH2 TIMER7_CH3 TIMER7_ ETI TIMER7_BKIN mapped on PC6 PC7 PC8 PC9 PA0 PA6 1 TIMER7_CH0 TIMER7_CH1 TIMER7_CH2 TIMER7_CH3 TIMER7_ ETI TIMER7_BKIN remapped to PI5 PI6 PI7 PI2 PI3 PI4 5 4 TIMER7_CHON_RE MAP 1 0 TIMER7_CH0_ON TIMER7__CH1_ON TIMER7_CH2_ON remapping This bit is set and cleared by sof...

Page 182: ...pping 1 This bit is set and cleared by software 0 No remap 1 I2C2_SCL I2C2_SDA I2C2_SMBA remapped to PH7 PH8 PH9 0 I2C2_REMAP0 I2C2 remapping 0 This bit is set and cleared by software 0 No remap 1 I2C2_SCL I2C2_SDA I2C2_ SMBA remapped to PA8 PC9 PA9 ...

Page 183: ... AHB clock cycles for 32 bit input data size from data entered to the calculation result available Free 8 bit register is unrelated to calculation and can be used for any other goals by any other peripheral devices Fixed polynomial 0x4C11DB7 X32 X26 X23 X22 X16 X12 X11 X10 X8 X7 X5 X4 X2 X 1 This 32 bit CRC polynomial is a common polynomial used in Ethernet Figure 8 1 Block diagram of CRC calculat...

Page 184: ...software setting the CRC_CTL register the new input raw data will be calculated based on the result of previous value of CRC_DATA CRC calculation will spend 4 AHB clock cycles for 32 bit data size during this period AHB will not be hanged because of the existence of the 32 bit input buffer This module supplies an 8 bit free register CRC_FDATA CRC_FDATA is unrelated to the CRC calculation any value...

Page 185: ... Software writes and reads This register is used to calculate new data and the register can be written the new data directly Written value cannot be read because the read value is the previous CRC calculation result 8 4 2 Free data register CRC_FDATA Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ...

Page 186: ...eset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RST rs Bits Fields Descriptions 31 1 Reserved Keep at reset value 0 RST Set this bit can reset the CRC_DATA register to the value of 0xFFFFFFFF then automatically cleared itself to 0 by hardware This bit will take no effect t...

Page 187: ...hip power consumption 32 bit random value seed is generated from analog noise so the random number is a true random number 9 3 Function overview Figure 9 1 TRNG block diagram AHB 32 bit Bus TRNG_CTL TRNG_STAT TRNG_DATA LFSR Clock Check Analog Seed TRNG_CLK Seed Check HCLK The random number seed comes from analog circuit This analog seed is then plugged into a linear feedback shift register LFSR wh...

Page 188: ...3 When an interrupt occurs check the status register TRGN_STAT if SEIF 0 CEIF 0 and DRDY 1 then the random value in the data register could be read As required by the FIPS PUB 140 2 the first random data in data register should be saved but not be used Every subsequent new random data should be compared to the previously random data The data can only be used if it is not equal to the previously on...

Page 189: ...t at reset value 3 IE Interrupt enabled bit This bit controls the generation of an interrupt when DRDY SEIF or CEIF was set 0 TRNG Interrupt disable 1 TRNG Interrupt enable 2 TRNGEN TRNG enabled bit 0 TRNG module disable reduce power consuming 1 TRNG module enable 1 0 Reserved Must be kept at reset value 9 4 2 Status register TRNG_STAT Address offset 0x04 Reset value 0x0000 0000 This register has ...

Page 190: ...ror is detected at current time if more than 64 consecutive same bits or more than 32 consecutive 01 or 10 changing are detected 1 CECS Clock error current status 0 Clock error is not detected at current time In case of CEIF 1 and CECS 0 it means clock error has been detected before but now is recovered 1 Clock error is detected at current time TRNG_CLK frequency is lower than 1 16 HCLK frequency ...

Page 191: ...GD32F20x User Manual 191 Bits Fields Descriptions 31 0 TRNDATA 31 0 32 Bit Random data ...

Page 192: ...are supported to perform data encryption and decryption in the CAU in multiple modes The CAU is a 32 bit peripheral DMA transfer is supported and data can be accessed in the input and output FIFO 10 2 Characteristics DES TDES and AES encryption decryption algorithms are supported Multiple modes are supported respectively in DES TDES and AES including Electronic codebook ECB Cipher block chaining C...

Page 193: ...graphic acceleration processor The same swapping operation should be also performed on the processor output data before they are collected Note the least significant data always occupies the lowest address location no matter which data type is configured because the system memory is little endian Figure 10 1 DATAM No swapping and Half word swapping and Figure 10 2 DATAM Byte swapping and Bit swapp...

Page 194: ...ed in CBC and CTR modes to XOR with data blocks They are independent of plaintext and ciphertext and the DATAM value will not affect them Note the initialization vector registers CAU_IV0 1 H L can only be written when BUSY is 0 otherwise the write operations are invalid 10 4 Cryptographic acceleration processor The cryptographic acceleration unit implements DES and AES acceleration processors whic...

Page 195: ... configured three different keying options are allowed 1 Three same keys The three keys KEY3 KEY2 and KEY1 are completely equal which means KEY3 KEY2 KEY1 FIPS PUB 46 3 1999 and ANSI X9 52 1998 refers to this option It is easy to understand that this mode is equivalent to DES 2 Two different keys In this option KEY2 is different from KEY1 and KEY3 is equal to KEY1 which means KEY1 and KEY2 are ind...

Page 196: ...trated in Figure 10 4 DES TDES ECB encryption Figure 10 4 DES TDES ECB encryption SWAP CAU_DI DATAM DEA encrypt DEA encrypt DEA decrypt KEY1 KEY2 KEY3 SWAP CAU_DO Plaintext Ciphertext DES TDES ECB decryption The 64 bit input ciphertext is first obtained after data swapping according to the data type When the TDES algorithm is configured the input data block is read in the DEA and decrypted using K...

Page 197: ...n decrypted using KEY2 After that the output is fed back directly to the last DEA and encrypted with KEY3 The result is then used as the next initialization vector and exclusive ORed with the next plaintext data block to process next encryption The above operations are repeated until the last plaintext block is encrypted Note if the plaintext message does not consist of an integral number of data ...

Page 198: ... XORed with the initialization vector which is the same as that used during encryption At the same time the first ciphertext is then used as the next initialization vector and exclusive ORed with the next result after DEA blocks The above operations are repeated until the last ciphertext block is decrypted Note if the ciphertext message does not consist of an integral number of data blocks the fin...

Page 199: ...3 KEY2 when the key size is configured as 128 KEY3 KEY2 KEY1 when the key size is configured as 192 and KEY3 KEY2 KEY1 KEY0 when the key size is configured as 256 The thorough explanation of the key used in the AES is provided in FIPS PUB 197 November 26 2001 and the explanation process is omitted in this manual AES ECB mode encryption The 128 bit input plaintext is first obtained after data swapp...

Page 200: ...ration is then used as the first round key in the decryption After the key derivation the 128 bit input ciphertext is first obtained after data swapping according to the data type The input data block is read in the AEA and decrypted using keys prepared above The output is then swapped back according to the data type again and a 128 bit plaintext is produced The procedure of AES ECB mode decryptio...

Page 201: ...e 10 10 AES CBC encryption SWAP CAU_DI DATAM AEA encrypt CAU_KEY0 3 SWAP CAU_DO Plaintext Ciphertext CAU_IV0 1 H L AES CBC mode decryption Similar to that in AES ECB mode decryption the key derivation also must be completed first to prepare the decryption keys the input of the key schedule should be the same to that used in encryption The last round key obtained from the above operation is then us...

Page 202: ...on the key schedule during the encryption and decryption are the same Then decryption operation acts exactly in the same way as the encryption operation Only the 32 bit LSB of the 128 bit initialization vector represents the counter which means the other 96 bits are unchanged during the operation and the initial value should be set to 1 Nonce is 32 bit single use random value and should be updated...

Page 203: ... the ALGM bit in the CAU_CTL register 6 Configure the encryption direction by writing 0 to the CAUDIR bit in the CAU_CTL register 7 Configure the initialization vectors by writing the CAU_IV0 1 registers 8 Flush the input FIFO and output FIFO by configure the FFLUSH bit in the CAU_CTL register when CAUEN is 0 9 Enable the CAU by set the CAUEN bit as 1 in the CAU_CTL register 10 If the INF bit in t...

Page 204: ...n the CAU_CTL register 13 If the INF bit in the CAU_STAT0 register is 1 then write data blocks into the CAU_DI register The data can be transferred by DMA CPU during interrupts no DMA or interrupts 14 Wait for ONE bit in the CAU_STAT0 register is 1 then read the CAU_DO registers The output data can also be transferred by DMA CPU during interrupts no DMA or interrupts 15 Repeat steps 13 14 until al...

Page 205: ...t the value of CAUEN will never affect the situation of OSTA and OINTF 10 8 CAU suspended mode It is possible to suspend a data block if another new data block with a higher priority needs to be processed in CAU The following steps can be performed to complete the encryption decryption acceleration of the suspended data blocks When DMA transfer is used 1 Stop the current input transfer Clear the D...

Page 206: ...e message is suspended at the end of a block processing 2 Disable the CAU by clearing the CAUEN bit in the CAU_CTL register 3 Save the configuration including the key size data type operation mode direction and the key values When it is CBC or CTR chaining mode the initialization vectors should also be stored 4 Configure and process the new data block 5 Restore the process before Configure the CAU...

Page 207: ...t keep the reset value 15 CAUEN CAU Enable 0 CAU is disabled 1 CAU is enabled Note the CAUEN can be cleared automatically when the key derivation ALGM 111b is finished 14 FFLUSH Flush FIFO 0 No effect 1 When CAUEN 1 flush the input and output FIFO Reading this bit always returns 0 13 10 Reserved Must keep the reset value 9 8 KEYM 1 0 AES key size mode configuration must be configured when BUSY 0 0...

Page 208: ...th CAU_KEY0 1 2 3 Initialization vectors CAU_IV0 1 are used to XOR with data blocks In this mode encryption and decryption are same then the CAUDIR is disregarded 111 AES key derivation for decryption mode The input key must be same to that used in encryption The BUSY bit is set until the process has been finished and CAUEN is then cleared 2 CAUDIR CAU direction must be configured when BUSY 0 0 en...

Page 209: ... 0x08 Reset value 0x0000 0000 The data input register is used to transfer plaintext or ciphertext blocks into the input FIFO for processing The MSB is firstly written into the FIFO and the LSB is the last one If the CAUEN is 0 and the input FIFO is not empty when it is read then the first data in the FIFO is popped out and returned If the CAUEN is 1 the returned value is undefined Once it is read ...

Page 210: ... 2 1 0 DO 15 0 r Bits Fields Descriptions 31 0 DO 31 0 Data output These bits are read only read these bits return OUT FIFO value 10 9 5 CAU DMA enable register CAU_DMAEN Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DMAOEN DMAIEN rw rw Bits Fields D...

Page 211: ...interrupt is disable 1 OUT FIFO interrupt is enable 0 IINTEN IN FIFO interrupt enable 0 IN FIFO interrupt is disable 1 IN FIFO interrupt is enable 10 9 7 CAU Status register 1 CAU_STAT1 Address offset 0x18 Reset value 0x0000 0001 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OSTA ISTA r r Bits...

Page 212: ...FO enabled interrupt flag 0 IN FIFO Interrupt not pending 1 IN FIFO Interrupt pending when CAUEN is 1 10 9 9 CAU key registers CAU_KEY0 3 H L Address offset 0x20 to 0x3C Reset value 0x0000 0000 This registers have to be accessed by word 32 bit and all of them must be written when BUSY is 0 In DES mode only CAU_KEY1 is used In TDES mode CAU_KEY1 CAU_KEY2 and CAU_KEY3 are used In AES 128 mode KEY2H ...

Page 213: ...5 24 23 22 21 20 19 18 17 16 KEY0H 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY0H 15 0 w CAU_KEY0L Address offset 0x24 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY0L 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY0L 15 0 w CAU_KEY1H Address offset 0x28 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY1H 31 16 w 15 14 13 12 11 10 9 8 7...

Page 214: ...AU_KEY2L Address offset 0x34 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY2L 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY2L 15 0 w CAU_KEY3H Address offset 0x38 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY3H 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY3H 15 0 w CAU_KEY3L Address offset 0x3C Reset value 0x0000 0000 31 30 29 28 2...

Page 215: ...S mode IV0H is the leftmost bits and IV0L is the rightmost bits of the initialization vectors In AES mode IV0H is the leftmost bits and IV1L is the rightmost bits of the initialization vectors CAU_IV0H Address offset 0x40 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IV0H 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV0H 15 0 rw CAU_IV0L Address offset 0x44 Reset value ...

Page 216: ... 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV1H 15 0 rw CAU_IV1L Address offset 0x4C Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IV1L 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV1L 15 0 rw Bits Fields Descriptions 31 0 IV0 1 H L The initialization vector for DES TDES AES ...

Page 217: ...st for Comments number 1321 IETF RFC 1321 specifications MD5 11 2 Characteristics 32 bit AHB slave peripheral High performance of computation of hash algorithms Little endian data representation Multiple data types are supported including no swapping half word swapping byte swapping and bit swapping with 32 bit data words Automatic data padding to fill the 512 bit message block for digest computat...

Page 218: ...ord2 word3 A0 B0 A1 B1 A2 B2 A3 B3 B0 A0 B1 A1 B2 A2 B3 A3 Half word swapping No swapping WORD 0 MSB WORD 1 WORD 2 WORD 3 LSB WORD 0 MSB WORD 1 WORD 2 WORD 3 LSB Figure 11 2 DATAM Byte swapping and Bit swapping Byte swapping A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 D3 D2 D1 D0 A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3 D0 D1 D2 D3 WORD 0 MSB Bit swapping A31 A1 A0 B31 B1 B0 C31 C1 C0 D31 D1 D0 A0 A1 A31 B0 B1...

Page 219: ...tionally impossible and the result will be completely different with any change to the input message Figure 11 3 HAU block diagram AHB BUS Input FIFO 16 32 HAU_DI HAU_DO Data swapping Config Hash acceleration core SHA 1 SHA 224 SHA 256 MD5 Hash HMAC HAU_CTL HAU_STAT HAU_CFG HAU_INTEN 11 4 1 Automatic data padding The input message should be padded first so that the number of bits in the input of t...

Page 220: ...al must obtain the information as to whether the HAU_DI register contains the last bits of the message or not This can be confirmed with the status of the input FIFO and the HAU_DI register When DMA is used to transfer data The status of the block transfer is automatically interpreted with the information from the DMA controller And padding and digest computation are performed automatically as if ...

Page 221: ...ipad XOR 0x36 input where ipad and opad are used to extend the key to 512 bits with several 0 and is the concatenation operator There are four different phases in the HMAC mode 1 Configure the HMS bit in the HAU_CTL register as 1 and set the ALGM bits as the desired algorithm If the key size is longer than 64 bytes then the KLM bit in the HAU_CTL register should also be set After that start the HA...

Page 222: ...FO then DINT is asserted Note if the input FIFO interrupt is disenabled by DIIE with a 0 value the DINT is always de asserted Calculation completion interrupt The calculation completion interrupt is asserted when the digest calculation is finished then CINT is asserted Note if the calculation completion interrupt is disenabled by CCIE with a 0 value the CINT is always de asserted ...

Page 223: ...ode 0 Key length 64 bytes 1 Key length 64 bytes Note this bit must be changed when no computation is processing 15 14 Reserved Must keep the reset value 13 MDS Multiple DMA Selection Set this bit if hash message is large files and multiple DMA transfers are needed 0 Single DMA transfers needed and CALEN bit is automatically set at the end of a DMA transfer 1 Multiple DMA transfers needed and CALEN...

Page 224: ...tes swapping The data written into HAU_DI need bytes swapping before write to FIFO 11 bit swapping The data written into HAU_DI need bytes swapping before write to FIFO 3 DMAE DMA enable 0 DMA disabled 1 DMA enabled Note 1 this bit is cleared when transferring the last data of the message but not cleared because of START 2 When DMA is transferring writing 0 to this bit will not stop the current tr...

Page 225: ...Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CALEN Reserved VBL 4 0 w rw Bits Fields Descriptions 31 9 Reserved Must keep the reset value 8 CALEN Digest calculation enable 0 No calculation 1 Start data padding with VBL prepared previously Start the calculation of the last digest Note reading this bit always returns 0 7 5 Reserved Must keep the reset value 4 0 VBL 4 0 Valid bits length i...

Page 226: ...ART bit Any read access when calculating will be extended until the calculation is completed In SHA 1 mode HAU_DO0 4 are used In MD5 mode HAU_DO0 3 are used In SHA 224 mode HAU_DO0 6 are used In SHA 256 mode HAU_DO0 7 are used HAU_DO0 Address offset 0x0C and 0x310 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DO0 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DO0 15 0 r HAU_DO1 Address offset 0x1...

Page 227: ...HAU_DO4 Address offset 0x1C and 0x320 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DO4 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DO4 15 0 r HAU_DO5 Address offset 0x324 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DO5 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DO5 15 0 r HAU_DO6 Address offset 0x328 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DO6 31 16 r 15 14 13 12 11 10 9 8 7 6 ...

Page 228: ...5 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CCIE DIIE rw rw Bits Fields Descriptions 31 2 Reserved Must keep the reset value 1 CCIE Calculation completion interrupt enable 0 Calculation completion interrupt is disabled 1 Calculation completion interrupt is enabled 0 DIIE Data input interrupt enable 0 Data input interrupt is disabled 1 Data input interrupt i...

Page 229: ...tatus 0 DMA is disabled DMAE 0 and no transfer is processing 1 DMA is enabled DMAE 1 or a transfer is processing 1 CINT Digest calculation completion interrupt flag 0 Digest calculation is not completed 1 Digest calculation is completed Note this bit will be cleared if CCIE 0 0 DINT Data input interrupt flag 0 There is no enough space 16 bytes in the input FIFO 1 There is enough space 16 bytes in ...

Page 230: ...us bandwidth for the CPU 12 2 Characteristics Programmable length of data to be transferred max to 65536 14 channels and each channel are configurable 7 for DMA0 and 7 for DMA1 AHB and APB peripherals FLASH SRAM can be accessed as source and destination Each channel is connected to fixed hardware DMA request Software DMA channel priority low medium high ultra high and hardware DMA channel priority...

Page 231: ...ent to control address data selection and data counting 12 4 Function overview 12 4 1 DMA operation Each DMA transfer consists of two operations including the loading of data from the source and the storage of the loaded data to the destination The source and destination addresses are computed by the DMA controller based on the programmed values in the DMA_CHxPADDR DMA_CHxMADDR and DMA_CHxCTL regi...

Page 232: ... 1 Read B3B2B1B0 31 0 0x0 2 Read B7B6B5B4 31 0 0x4 3 Read BBBAB9B8 31 0 0x8 4 Read BFBEBDBC 31 0 0xC 1 Write B1B0 7 0 0x0 2 Write B5B4 7 0 0x2 3 Write B9B8 7 0 0x4 4 Write BDBC 7 0 0x6 32 bits 8 bits 1 Read B3B2B1B0 31 0 0x0 2 Read B7B6B5B4 31 0 0x4 3 Read BBBAB9B8 31 0 0x8 4 Read BFBEBDBC 31 0 0xC 1 Write B0 7 0 0x0 2 Write B4 7 0 0x1 3 Write B8 7 0 0x2 4 Write BC 7 0 0x3 16 bits 32 bits 1 Read B...

Page 233: ... 2 Write B3B2 16 0 0x2 2 Read B7B6B5B4 31 0 0x4 1 Write B5B4 16 0 0x4 2 Write B7B6 16 0 0x6 32 bits 8 bits 1 Read B3B2B1B0 31 0 0x0 1 Write B0 7 0 0x0 2 Write B1 7 0 0x1 3 Write B2 7 0 0x2 4 Write B3 7 0 0x3 2 Read B7B6B5B4 31 0 0x4 1 Write B4 7 0 0x4 2 Wirte B5 7 0 0x5 3 Write B6 7 0 0x6 4 Write B7 7 0 0x7 NOTE The Full_Data transfer mode is only available for the channel 5 of DMA1 12 4 2 Periphe...

Page 234: ...w medium high and ultra high by configuring the PRIO bits in the DMA_CHxCTL register For channels with equal software priority level priority is given to the channel with lower channel number 12 4 4 Address generation Two kinds of address generation algorithm are implemented independently for memory and peripheral including the fixed mode and the increased mode The PNAGA and MNAGA bit in the DMA_C...

Page 235: ...fer width memory and peripheral address generation algorithm in the DMA_CHxCTL register 6 Configure the enable bit for full transfer finish interrupt half transfer finish interrupt transfer error interrupt in the DMA_CHxCTL register 7 Configure the DMA_CHxPADDR register for setting the peripheral base address 8 Configure the DMA_CHxMADDR register for setting the memory base address 9 Configure the...

Page 236: ...al requests from peripherals may be mapped to one DMA channel They are logically ORed before entering the DMA For details see the following Figure 12 4 DMA0 request mapping and Figure 12 5 DMA1 request mapping The request of each peripheral can be independently enabled or disabled by programming the registers of the corresponding peripheral The user has to ensure that only one request is enabled a...

Page 237: ...TOMEM4 MEMTOMEM3 SPI1 I2S1_TX USART0_RX I2C1_RX TIMER0_UP TIMER1_CH0 TIMER3_CH2 or or Channel 4 MEMTOMEM4 USART1_RX I2C0_TX TIMER0_CH2 TIMER2_CH0 TIMER2_TG or or Channel 5 MEMTOMEM6 MEMTOMEM5 USART1_TX I2C0_RX TIMER1_CH1 TIMER1_CH3 TIMER3_UP or or Channel 6 MEMTOMEM6 Table 12 4 DMA0 requests for each channel Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 TIMER0 TI...

Page 238: ..._CH2 TIMER7_UP or or Channel 0 MEMTOMEM0 Hardware priority high low SPI2 I2S2_TX UART4_RX UARR7_RX TIMER4_CH2 TIMER4_UP TIMER7_CH3 TIMER7_TG TIMER7_CMT or or Channel 1 MEMTOMEM2 MEMTOMEM1 UART3_RX UART6_RX TIMER5_UP DAC_CH0 TIMER7_CH0 or or Channel 2 MEMTOMEM2 UART4_TX UART7_TX SDIO TIMER4_CH1 TIMER6_UP DAC_CH1 or or Channel 3 MEMTOMEM4 MEMTOMEM3 ADC2 UART3_TX UART6_TX TIMER4_CH0 TIMER7_CH1 or or ...

Page 239: ... TIMER4_UP TIMER4_CH1 TIMER4_CH0 TIMER5 DAC_ CH0 TIMER5_UP DAC_CH0 TIMER6 DAC_ CH1 TIMER6_UP DAC_CH1 TIMER7 TIMER7_CH2 TIMER7_UP TMER7_CH3 TMER7_TG TMER7_CMT TMER7_CH0 TMER7_CH1 ADC2 ADC2 SPI I2S SPI2 I2S2_RX SPI2 I2S2_TX USART UART4_RX UART7_RX UART3_RX UART6_RX UART4_TX UART7_TX UART3_TX UART6_TX USART5_RX USART5_TX SDIO SDIO I2C2 I2C2_TX I2C2_RX DCI DCI CAU CAU_OUT CAU_IN HAU HAU_IN ...

Page 240: ...A_INTC register 0 Transfer error has not occurred on channel x 1 Transfer error has occurred on channel x 26 22 18 14 10 6 2 HTFIFx Half transfer finish flag of channel x x 0 6 Hardware set and software cleared by configuring DMA_INTC register 0 Half number of transfer has not finished on channel x 1 Half number of transfer has finished on channel x 25 21 17 13 9 5 1 FTFIFx Full Transfer finish fl...

Page 241: ... x 0 6 0 No effect 1 Clear half transfer finish flag 25 21 17 13 9 5 1 FTFIFCx Clear bit for full transfer finish flag of channel x x 0 6 0 No effect 1 Clear full transfer finish flag 24 20 16 12 8 4 0 GIFCx Clear global interrupt flag of channel x x 0 6 0 No effect 1 Clear GIFx ERRIFx HTFIFx and FTFIFx bits in the DMA_INTF register 12 5 3 Channel x control register DMA_CHxCTL x 0 6 where x is a c...

Page 242: ...ared 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits can not be written when CHEN is 1 7 MNAGA Next address generation algorithm of memory Software set and cleared 0 Fixed address mode 1 Increasing address mode This bit can not be written when CHEN is 1 6 PNAGA Next address generation algorithm of peripheral Software set and cleared 0 Fixed address mode 1 Increasing address mode This bit can n...

Page 243: ...inish interrupt 0 CHEN Channel enable Software set and cleared 0 Disable channel 1 Enable channel 12 5 4 Channel x counter register DMA_CHxCNT x 0 6 where x is a channel number Address offset 0x0C 0x14 x Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits Fields Descriptions 31 16 Reserved Keep at reset value 15 0 ...

Page 244: ...ss is automatically aligned to a half word address When PWIDTH is 10 32 bit the two LSBs of these bits are ignored Access is automatically aligned to a word address 12 5 6 Channel x memory base address register DMA_CHxMADDR x 0 6 where x is a channel number Address offset 0x14 0x14 x Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MADDR 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 ...

Page 245: ...8 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FD_CH5EN Reserved rw Bits Fields Descriptions 31 6 Reserved must be kept at reset value 5 FD_CH5EN Enable bit for channel 5 Full_Data transfer mode This bit can not be written when CHEN in the DMA_CHxCTL register is 1 0 Disable the channel 5 Full_Data transfer mode 1 Enable the channel 5 Full_Data transfe...

Page 246: ...r TIMER WWDGT FWDGT I2C or CAN 13 2 JTAG SW characteristics Debug capabilities can be accessed by a debug tool via Serial Wire SW Debug Port or JTAG interface JTAG Debug Port 13 2 1 Switch JTAG or SW interface By default the JTAG interface is active The sequence for switching from JTAG to SWD is Send 50 or more TCK cycles with TMS 1 Send the 16 bit sequence on TMS 1110011110011110 0xE79E LSB first...

Page 247: ...hift step it first shift 5 bit BYPASS instruction 5 b 11111 for BSD JTAG and then shift normal 4 bit instruction for Cortext M3 JTAG Because of the data shift under BSD JTAG BYPASS mode adding 1 extra bit to the data chain is needed The BSD JTAG IDCODE is 0x790007A3 13 2 4 Debug reset The JTAG DP and SW DP register are in the power on reset domain The System reset initializes the majority of the C...

Page 248: ...D bit in DBG control register DBG_CTL is set and entering the sleep mode the clock of AHB bus for CPU is not closed and the debugger can debug in sleep mode 13 3 2 Debug support for TIMER I2C WWDGT FWDGT and CAN When the core halted and the corresponding bit in DBG control register 1 DBG_CTL is set the following behaved For TIMER the timer counters stopped and hold for debug For I2C SMBUS timeout ...

Page 249: ...7 26 25 24 23 22 21 20 19 18 17 16 Reserved TIMER10 _HOLD TIMER9_ HOLD TIMER8_ HOLD TIMER13 _HOLD TIMER12 _HOLD TIMER11 _HOLD Reserved CAN1_H OLD TIMER7_ HOLD TIMER6_ HOLD TIMER5_ HOLD TIMER4_ HOLD I2C1_HO LD rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2C0_HO LD CAN0_H OLD TIMER3_ HOLD TIMER2_ HOLD TIMER1_ HOLD TIMER0_ HOLD WWDGT_ HOLD FWDGT_ HOLD TRACE _MODE TRACE _...

Page 250: ...t 1 hold the TIMER 11 counter for debug when core halted 24 22 Reserved Must be kept at reset value 21 CAN1_HOLD CAN1 hold bit This bit is set and reset by software 0 no effect 1 the receive register of CAN1 stops receiving data when core halted 20 TIMER7_HOLD TIMER 7 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER 7 counter for debug when core halted 19 TIMER6_HOLD TIM...

Page 251: ...set and reset by software 0 no effect 1 hold the TIMER 2 counter for debug when core halted 11 TIMER1_HOLD TIMER 1 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER 1 counter for debug when core halted 10 TIMER0_HOLD TIMER 0 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER 0 counter for debug when core halted 9 WWDGT_HOLD WWDGT hold bit This bit...

Page 252: ...e 2 STB_HOLD Standby mode hold register This bit is set and reset by software 0 no effect 1 At the standby mode the clock of AHB bus and system clock are provided by CK_IRC8M a system reset generated when exit standby mode 1 DSLP_HOLD Deep sleep mode hold register This bit is set and reset by software 0 no effect 1 At the Deep sleep mode the clock of AHB bus and system clock are provided by CK_IRC...

Page 253: ... related computational burden from the MCU 14 2 Characteristics High performance 12 bit 10 bit 8 bit or 6 bit configurable resolution ADC sampling rate 2 MSPs for 12 bit resolution faster sampling rate can be obtained by lowering the resolution Self calibration Programmable sampling time Data alignment with built in data coherency DMA support Analog input channels 16 external analog inputs 1 chann...

Page 254: ...name Signal type Description VSENSE Input Internal temperature sensor output voltage VREFINT Input Internal voltage reference output voltage Table 14 2 ADC pins definition Name Signal type Remarks VDDA Input analog power supply Analog power supply equal to VDD and 2 6 V VDDA 3 6 V VSSA Input analog power supply ground Ground for analog power supply equal to VSS VREFP Input analog reference positiv...

Page 255: ...bration feature During the procedure the ADC calculates a calibration factor which is internally applied to the ADC until the next ADC power off The application must not use the ADC during calibration and must wait until it is completed Calibration should be performed before starting A D conversion The calibration is initiated by software by setting bit CLB 1 CLB bit stays at 1 during all the cali...

Page 256: ...p a sequence of up to 16 conversions can be organized in a specific sequence The ADC_RSQ0 ADC_RSQ2 registers specify the selected channels of the regular group The RL 3 0 bits in the ADC_RSQ0 register specify the total conversion sequence length In the inserted group a sequence of up to 4 conversions can be organized in a specific sequence The ADC_ISQ register specify the selected channels of the ...

Page 257: ...l number 3 Configure ADC_SAMPTx register 4 Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need 5 Set the SWRCST bit or generate an external trigger for the regular group 6 Wait the EOC flag to be set 7 Read the converted in the ADC_RDATA register 8 Clear the EOC flag by writing 0 to it Software procedure for a single conversion of an inserted channel 1 Make sure the DISIC SM in the ...

Page 258: ...C flag to be set 7 Read the converted in the ADC_RDATA register 8 Clear the EOC flag by writing 0 to it 9 Repeat steps 6 8 as soon as the conversion is in need To get rid of checking DMA can be used to transfer the converted data 1 Set the CTN and DMA bit in the ADC_CTL1 register 2 Configure RSQ0 with the analog channel number 3 Configure ADC_SAMPTx register 4 Configure ETERC and ETSRC bits in the...

Page 259: ...erted group IL 4 Regular trigger Sample Convert CH12 CH17 Software procedure for scan conversion on a regular channel group 1 Set the SM bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register 2 Configure ADC_RSQx and ADC_SAMPTx registers 3 Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need 4 Prepare the DMA module to transfer data from the ADC_RDATA 5 Set the SWRCST ...

Page 260: ...serted channel group the discontinuous conversion mode will be enabled when DISIC bit in the ADC_CTL0 register is set In this mode the ADC performs one conversion which is a part of the sequence of conversions selected in the ADC_ISQ register When the corresponding software trigger or external trigger is active the ADC samples and coverts the next channel selected in the ADC_ISQ register until all...

Page 261: ...egister if in need 4 Set the SWICST bit or generate an external trigger for the inserted group 5 Repeat step4 if in need 6 Wait the EOC EOIC flags to be set 7 Read the converted in the ADC_IDATAx register 8 Clear the EOC EOIC flag by writing 0 to them 14 4 6 Inserted channel management Auto insertion The inserted group channels are automatically converted after the regular group channels when the ...

Page 262: ...threshold or above a high threshold the WDE bit in ADC_STAT register will be set An interrupt will be generated if the WDEIE bit is set The ADC_WDHT and ADC_WDLT registers are used to specify the high and low threshold The comparison is done before the alignment so the threshold value is independent of the alignment which is specified by the DAL bit in the ADC_CTL1 register One or more channels wh...

Page 263: ...it resolution Sign Sign Sign Sign D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 Regular group data Inserted group data 0 0 0 Sign 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Regular group data Inserted group data DAL 0 DAL 1 Figure 14 11 Data alignment of 8 bit resolution Sign Sign Sign Sign D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 D7 D6...

Page 264: ...le time is 1 5 cycles the total conversion time is 1 5 12 5 ADCCLK cycles that means 1us 14 4 10 External trigger The conversion of regular or inserted group can be triggered by rising edge of external trigger inputs The external trigger source of regular channel group is controlled by the ETSRC 2 0 bits in the ADC_CTL1 register while the external trigger source of inserted channel group is contro...

Page 265: ...r Table 14 6 External trigger for inserted channels for ADC2 ETSIC 2 0 Trigger Source Trigger Type 000 TIMER0_TRGO Internal on chip signal 001 TIMER0_CH3 010 TIMER3_CH2 011 TIMER7_CH1 100 TIMER7_CH3 101 TIMER4_TRGO 110 TIMER4_CH3 111 SWICST Software trigger 14 4 11 DMA request The DMA request which is enabled by the DMA bit of ADC_CTL1 register is used to transfer data of regular group for convers...

Page 266: ... VREFINT is internally connected to the ADC0_CH17 input channel Software procedure for use the temperature sensor 1 Configure the conversion sequence ADC_IN16 and the sampling time 17 1μs for the channel 2 Enable the temperature sensor by setting the TSVREN bit in the ADC control register 1 ADC_CTL1 3 Start the ADC conversion by setting the ADCON bit or by external trigger 4 Read the resulting tem...

Page 267: ...al signal of the ADC Result 1 M Dout n N 1 n 0 12 1 The on chip hardware oversampling circuit performs the following functions summing and bit right shifting The oversampling ratio N is defined by the OVSR 2 0 bits in the ADC_OVSAMPCTL register It can range from 2x to 256x The division coefficient M means bit right shifting up to 8 bit It is configured through the OVSS 3 0 bits in the ADC_OVSAMPCT...

Page 268: ...ft OVSS 0101 6 bit shift OVSS 0110 7 bit shift OVSS 0111 8 bit shift OVSS 1000 2x 0x1FFE 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 0x003F 0x001F 4x 0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 0x003F 8x 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 16x 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 32x 0x1FFE0 0xFFE0 0xFFF0 0x...

Page 269: ... triggers to start unwanted conversion However the external trigger must be enabled for ADC master and ADC slave The following modes can be configured Free mode Regular parallel mode Inserted parallel mode Follow up fast mode Follow up slow mode Trigger rotation mode Inserted parallel mode regular parallel mode Regular parallel mode trigger rotation mode Inserted parallel mode follow up fast mode ...

Page 270: ...e regular group MUX of ADC0 selected by the ETSRC 2 0 bits in the ADC_CTL1 register A simultaneous trigger is provided to ADC1 At the end of conversion event on ADC0 or ADC1 an EOC interrupt is generated if enabled on one of the two ADC interfaces when the ADC0 ADC1 regular channels are all converted The behavior of regular parallel mode shows in the Figure 14 16 Regular parallel mode on 16 channe...

Page 271: ...interface The behavior of inserted parallel mode shows in the Figure 14 17 Inserted parallel mode on 4 channels Note 1 Do not convert the same channel on the two ADCs no overlapping sampling times for the two ADCs when converting the same channel 2 In parallel mode exactly the same sampling time should be configured for the two channels that will be sampled simultaneously by ADC0 and ADC1 Figure 1...

Page 272: ...g on the regular channel group usually one channel The source of external trigger comes from the regular channel MUX of ADC0 selected by the ETSRC 2 0 bits in the ADC_CTL1 register When the trigger occurs ADC1 runs immediately ADC0 runs after 14 ADC clock cycles after the second 14 ADC clock cycles the ADC1 runs again Continuous mode can t be used in this mode because it continuously converts the ...

Page 273: ... of ADC0 or ADC1 have been converted the corresponded interrupt occurred If another external trigger occurs after all inserted group channels have been converted the trigger rotation process restarts by converting ADC0 inserted group channels Figure 14 20 Trigger rotation inserted channel group Inserted trigger Channel group Channel group EOIC ADC0 Sample Convert Channel group Channel group ADC0 A...

Page 274: ... 8 Combined regular parallel trigger rotation mode It is possible to interrupt regular group parallel conversion to start trigger rotation conversion of an inserted group The behavior of an alternate trigger interrupt a regular parallel conversion shows in the Figure 14 22 Regular parallel trigger rotation mode When the inserted event occurs the inserted rotation conversion is immediately started ...

Page 275: ...rrupted and the inserted conversion starts at the end of the inserted sequence the follow up conversion is resumed Figure 14 24 Follow up single channel with inserted sequence CH1 CH2shows the behavior of this mode Figure 14 24 Follow up single channel with inserted sequence CH1 CH2 CH0 CH0 CH0 CH2 CH1 CH1 CH2 ADC0 regular ADC0 inserted Inserted trigger Sample Convert CH0 CH0 CH0 ADC1 regular ADC1...

Page 276: ...r channel group started 1 Regular channel group started Set by hardware when regular channel conversion starts Cleared by software writing 0 to it 3 STIC Start flag of inserted channel group 0 No inserted channel group started 1 Inserted channel group started Set by hardware when inserted channel group conversion starts Cleared by software writing 0 to it 2 EOIC End of inserted group conversion fl...

Page 277: ...w rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 RWDEN Regular channel analog watchdog enable 0 Regular channel analog watchdog disable 1 Regular channel analog watchdog enable 22 IWDEN Inserted channel analog watchdog enable 0 Inserted channel analog watchdog disable 1 Inserted channel analog watchdog enable 21 20 Reserved Must be kept at reset valu...

Page 278: ...serted channel group convert automatically 0 Inserted channel group convert automatically disable 1 Inserted channel group convert automatically enable 9 WDSC When in scan mode analog watchdog is effective on a single channel 0 Analog watchdog is effective on all channels 1 Analog watchdog is effective on a single channel 8 SM Scan mode 0 scan mode disable 1 scan mode enable 7 EOICIE Interrupt ena...

Page 279: ...17 16 Reserved TSVREN SWRCST SWICST ETERC ETSRC 2 0 Reserved rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETEIC ETSIC 2 0 DAL Reserved DMA Reserved RSTCLB CLB CTN ADCON rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 TSVREN Channel 16 and 17 enable of ADC0 0 Channel 16 and 17 of ADC0 disable 1 Channel 16 and 17 of ADC0 enable 22 SWRCST Start o...

Page 280: ...imer 0 CH2 011 Timer 7 CH0 100 Timer 7 TRGO 101 Timer 4 CH0 110 Timer 4 CH2 111 SWRCST 16 Reserved Must be kept at reset value 15 ETEIC External trigger enable for inserted channel 0 External trigger for inserted channel disable 1 External trigger for inserted channel enable 14 12 ETSIC 2 0 External trigger select for inserted channel For ADC0 and ADC1 000 Timer 0 TRGO 001 Timer 0 CH3 010 Timer 1 ...

Page 281: ...tion done 1 Calibration start 1 CTN Continuous mode 0 Continuous mode disable 1 Continuous mode enable 0 ADCON ADC ON The ADC will be wake up when this bit is changed from low to high and take a stabilization time When this bit is high and 1 is written to it with other bits of this register unchanged the conversion will start 0 ADC disable and power down 1 ADC enable 14 7 4 Sample time register 0 ...

Page 282: ...tion 5 3 SPT11 2 0 refer to SPT10 2 0 description 2 0 SPT10 2 0 Channel sample time 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles 14 7 5 Sample time register 1 ADC_SAMPT1 Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved...

Page 283: ...er to SPT0 2 0 description 5 3 SPT1 2 0 refer to SPT0 2 0 description 2 0 SPT0 2 0 Channel sample time 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles 14 7 6 Inserted channel data offset register x ADC_IOFFx x 0 3 Address offset 0x14 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 2...

Page 284: ...served WDHT 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 WDHT 11 0 Analog watchdog high threshold These bits define the high threshold for the analog watchdog 14 7 8 Watchdog low threshold register ADC_WDLT Address offset 0x28 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13...

Page 285: ... group equals to RL 3 0 1 19 15 RSQ15 4 0 refer to RSQ0 4 0 description 14 10 RSQ14 4 0 refer to RSQ0 4 0 description 9 5 RSQ13 4 0 refer to RSQ0 4 0 description 4 0 RSQ12 4 0 refer to RSQ0 4 0 description 14 7 10 Regular sequence register 1 ADC_RSQ1 Address offset 0x30 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ...

Page 286: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSQ3 0 RSQ2 4 0 RSQ1 4 0 RSQ0 4 0 rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 25 RSQ5 4 0 refer to RSQ0 4 0 description 24 20 RSQ4 4 0 refer to RSQ0 4 0 description 19 15 RSQ3 4 0 refer to RSQ0 4 0 description 14 10 RSQ2 4 0 refer to RSQ0 4 0 description 9 5 RSQ1 4 0 refer to RSQ0 4 0 description 4 0 RSQ0 4 0 The channel numbe...

Page 287: ... 0 The channel number 0 17 is written to these bits to select a channel at the nth conversion in the inserted channel group Unlike the regular conversion sequence the inserted channels are converted starting from 4 IL 1 0 1 if IL 1 0 length is less than 4 IL Insert channel order 3 ISQ0 ISQ1 ISQ2 ISQ3 2 ISQ1 ISQ2 ISQ3 1 ISQ2 ISQ3 0 ISQ3 14 7 13 Inserted data register x ADC_IDATAx x 0 3 Address offs...

Page 288: ...e bits contain the regular data of ADC1 In ADC1 and ADC2 these bits are not used 15 0 RDATA 15 0 Regular channel data These bits contain the conversion result from regular channel which is read only 14 7 15 Oversample control register ADC_OVSAMPCTL Address offset 0x80 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15...

Page 289: ...0001 Shift 1 bit 0010 Shift 2 bits 0011 Shift 3 bits 0100 Shift 4 bits 0101 Shift 5 bits 0110 Shift 6 bits 0111 Shift 7 bits 1000 Shift 8 bits Other codes reserved Note Software is allowed to write this bit only when ADCON 0 which ensures that no conversion is ongoing 4 2 OVSR 2 0 Oversampling ratio This bit filed defines the number of oversampling ratio 000 2x 001 4x 010 8x 011 16x 100 32x 101 64...

Page 290: ...GD32F20x User Manual 290 conversion is ongoing ...

Page 291: ...tage can be optionally buffered for higher drive capability Two DACs can work independently or concurrently 15 2 Characteristics DAC s main features are as follows 12 bit resolution Left or right data alignment DMA capability for each channel Conversion update synchronously Conversion trigged by external triggers Configurable internal buffer Input voltage reference VREF Noise wave generation LFSR ...

Page 292: ...upply Input analog supply VSSA Ground for analog power supply Input analog supply ground VREF Positive reference voltage for the DAC 2 4 V VREF VDDA Input analog positive reference DAC_OUTx DACx analog output Analog output signal The GPIO pins PA4 for DAC0 PA5 for DAC1 should be configured to analog mode before enable the DAC module 15 3 Function overview 15 3 1 DAC enable The DACs can be powered ...

Page 293: ...signal 001 TIMER2_TRGO 010 TIMER6_TRGO 011 TIMER4_TRGO 100 TIMER1_TRGO 101 TIMER3_TRGO 110 EXTI_9 External signal 111 SWTRIG Software trigger The TIMERx_TRGO signals are generated from the timers while the software trigger can be generated by setting the SWTRx bits in the DAC_SWT register 15 3 5 DAC conversion If the external trigger is enabled by setting the DTENx bit in DAC_CTL register the DAC ...

Page 294: ... bits of the LFSR register Figure 15 2 DAC LFSR algorithm 9 7 8 6 5 4 3 2 1 11 10 0 X6 X0 X4 X XOR X12 NOR 12 In the triangle noise mode a triangle signal is added to the DACx_DH value The minimum value of the triangle signal is 0 while the maximum value of the triangle signal is 2 DWBWx 1 Figure 15 3 DAC triangle noise wave 2 DWBWx 1 DACx_DH value DACx_DH value 15 3 7 DAC output voltage The analo...

Page 295: ...e configured in concurrent mode In concurrent mode the DACx_DH and DACx_DO value will be updated at the same time There are three concurrent registers that can be used to load the DACx_DH value DACC_R8DH DACC_R12DH and DACC_L12DH You just need to access a unique register to realize driving both DACs at the same time When external trigger is enabled both DTENx bits should be set DTSEL0 and DTSEL1 b...

Page 296: ... noise wave signal of DAC1 These bits indicate that unmask LFSR bit n 1 0 in LFSR noise mode or the amplitude of the triangle is 2 n 1 1 in triangle noise mode where n is the bit width of wave 0000 The bit width of the wave signal is 1 0001 The bit width of the wave signal is 2 0010 The bit width of the wave signal is 3 0011 The bit width of the wave signal is 4 0100 The bit width of the wave sign...

Page 297: ...eset value 12 DDMAEN0 DAC0 DMA enable 0 DAC0 DMA mode disabled 1 DAC0 DMA mode enabled 11 8 DWBW0 3 0 DAC0 noise wave bit width These bits specify bit width of the noise wave signal of DAC0 These bits indicate that unmask LFSR bit n 1 0 in LFSR noise mode or the amplitude of the triangle is 2 n 1 1 in triangle noise mode where n is the bit width of wave 0000 The bit width of the wave signal is 1 0...

Page 298: ...GO 011 Timer 4 TRGO 100 Timer 1 TRGO 101 Timer 3 TRGO 110 EXTI line 9 111 Software trigger 2 DTEN0 DAC0 trigger enable 0 DAC0 trigger disabled 1 DAC0 trigger enabled 1 DBOFF0 DAC0 output buffer turn off 0 DAC0 output buffer turn on to reduce the output impedance and improve the driving capability 1 DAC0 output buffer turn off 0 DEN0 DAC0 enable 0 DAC0 disabled 1 DAC0 enabled 15 4 2 Software trigge...

Page 299: ... register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAC0_DH 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 DAC0_DH 11 0 DAC0 12 bit right aligned data These bits specify the data that is to be converted by DAC0 15 4 4 DAC0 12 bit left aligned data holding register DAC0_...

Page 300: ...rved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAC0_DH 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 DAC0_DH 7 0 DAC0 8 bit right aligned data These bits specify the MSB 8 bits of the data that is to be converted by DAC0 15 4 6 DAC1 12 bit right aligned data holding register DAC1_R12DH Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed...

Page 301: ...et value 15 4 DAC1_DH 11 0 DAC1 12 bit left aligned data These bits specify the data that is to be converted by DAC1 3 0 Reserved Must be kept at reset value 15 4 8 DAC1 8 bit right aligned data holding register DAC1_R8DH Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4...

Page 302: ...These bits specify the data that is to be converted by DAC1 15 12 Reserved Must be kept at reset value 11 0 DAC0_DH 11 0 DAC0 12 bit right aligned data These bits specify the data that is to be converted by DAC0 15 4 10 DAC concurrent mode 12 bit left aligned data holding register DACC_L12DH Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 ...

Page 303: ...erved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAC1_DH 7 0 DAC0_DH 7 0 rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 8 DAC1_DH 7 0 DAC1 8 bit right aligned data These bits specify the MSB 8 bit of the data that is to be converted by DAC1 7 0 DAC0_DH 7 0 DAC0 8 bit right aligned data These bits specify the MSB 8 bit of the data that is to be converted by DAC0 15 4 12 DAC...

Page 304: ...data output register DAC1_DO Address offset 0x30 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAC1_DO 11 0 r Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 DAC1_DO 11 0 DAC1 data output These bits which are read only reflect the data that is b...

Page 305: ...free clock source IRC40K Thereupon the FWDGT can operate even if the main clock fails It s suitable for the situation that requires an independent environment and lower timing accuracy The free watchdog timer causes a reset when the internal down counter reaches 0 The register write protection function in free watchdog can be enabled to prevent it from changing the configuration unexpectedly 16 1 ...

Page 306: ...set To avoid reset the software should reload the counter before the counter reaches 0x000 The FWDGT_PSC register and the FWDGT_RLD register are written protected Before writing these registers the software should write the value 0x5555 to the FWDGT_CTL register These registers will be protected again by writing any other value to the FWDGT_CTL register When an update operation of the prescaler re...

Page 307: ...anual 307 Prescaler divider PSC 2 0 bits Min timeout ms RLD 11 0 0x000 Max timeout ms RLD 11 0 0xFFF 1 128 101 3 2 13107 2 1 256 110 or 111 6 4 26214 4 The FWDGT timeout can be more accurate by calibrating the IRC40K ...

Page 308: ... values 0x5555 Disable the FWDGT_PSC and FWDGT_RLD write protection 0xCCCC Start the free watchdog counter When the counter reduces to 0 the free watchdog generates a reset 0xAAAA Reload the counter Prescaler register FWDGT_PSC Address offset 0x04 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved...

Page 309: ... 2 1 0 Reserved RLD 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 RLD 11 0 Free watchdog timer counter reload value Write 0xAAAA in the FWDGT_CTL register will reload the FWDGT counter with the RLD value These bits are write protected Write 0x5555 in the FWDGT_CTL register before writing these bits During a write operation to this register the RUD bit in the FWDG...

Page 310: ...alue update During a write operation to FWDGT_RLD register this bit is set and the value read from FWDGT_RLD register is invalid This bit is reset by hardware after the update operation of FWDGT_RLD register 0 PUD Free watchdog timer prescaler value update During a write operation to FWDGT_PSC register this bit is set and the value read from FWDGT_PSC register is invalid This bit is reset by hardw...

Page 311: ... watchdog timer clock is prescaled from the APB1 clock The window watchdog timer is suitable for the situation that requires an accurate timing 16 2 2 Charateristics Programmable free running 7 bit downcounter Generate reset in two conditions when WWDGT is enabled Reset when the counter reached 0x3F The counter is refreshed when the value of the counter is greater than the window register value Ea...

Page 312: ...ster WWDGT_CFG specifies the window value The software can prevent the reset event by reloading the downcounter when counter value is less than the window value and greater than 0x3F otherwise the watchdog causes a reset The early wakeup interrupt EWI is enabled by setting the EWIE bit in the WWDGT_CFG register and the interrupt is generated when the counter reaches 0x40 or the counter is refreshe...

Page 313: ...1 clock period measured in ms Refer to the table below for the minimum and maximum values of the tWWDGT Table 16 2 Min max timeout value at 60 MHz fPCLK1 Prescaler divider PSC 1 0 Min timeout value CNT 6 0 0x40 Max timeout value CNT 6 0 0x7F 1 1 00 68 2 μs 4 3ms 1 2 01 136 4 μs 8 6 ms 1 4 10 272 8μs 17 2 ms 1 8 11 545 6 μs 34 4 ms If the WWDGT_HOLD bit in DBG module is cleared the WWDGT continues ...

Page 314: ...hdog timer disabled 1 Window watchdog timer enabled 6 0 CNT 6 0 The value of the watchdog timer counter A reset occurs when the value of this counter decreases from 0x40 to 0x3F When the value of this counter is greater than the window value writing this counter also causes a reset Configuration register WWDGT_CFG Address offset 0x04 Reset value 0x0000 007F This register can be accessed by half wo...

Page 315: ...of the watchdog counter is greater than the Window value Status register WWDGT_STAT Address offset 0x08 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWIF rw Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 EWIF Early wakeup interrup...

Page 316: ...ain B RTC clock domain this clock must be at least 4 times slower than the PCLK1 clock RTC clock source A HXTAL clock divided by 128 B LXTAL oscillator clock C IRC40K oscillator clock Maskable interrupt source A Alarm interrupt B Second interrupt C Overflow interrupt 17 3 Function overview The RTC circuits consist of two major units APB interface located in PCLK1 clock domain and RTC core located ...

Page 317: ...PIEN bits in the RCU_APB1EN register to enable the power and backup interface clocks 2 Enable access to the backup registers and RTC by setting the BKPWEN bit in the PMU_CTL 17 3 2 RTC reading The APB interface and RTC core are located in two different power supply domains In the RTC core only counter and divider registers are readable registers And the values in the two registers and the RTC flag...

Page 318: ...L register E Wait until the value of LWOFF bit in the RTC_CTL register sets to 1 17 3 4 RTC flag assertion Before the update of the RTC Counter the RTC second interrupt flag SCIF is asserted on the last RTCCLK cycle Before the counter which is equal to the RTC Alarm value which stored in the Alarm register increases by one the RTC Alarm interrupt flag ALRMIF is asserted on the last RTCCLK cycle Be...

Page 319: ...19 Figure 17 3 RTC second and overflow waveform example RTC_PSC 3 RTC_ Overflow FFFFFFFD FFFFFFFE FFFFFFFF 0 1 RTC_Second RTC_ CNT OVIF RTC_PSC OVIF flag can be cleared by software RTCCLK 2 3 1 0 3 1 1 3 3 2 1 0 2 0 2 0 2 1 ...

Page 320: ...erved Must be kept at reset value 2 OVIE Overflow interrupt enable 0 Disable overflow interrupt 1 Enable overflow interrupt 1 ALRMIE Alarm interrupt enable 0 Disable alarm interrupt 1 Enable alarm interrupt 0 SCIE Second interrupt enable 0 Disable second interrupt 1 Enable second interrupt 17 4 2 RTC control register RTC_CTL Address offset 0x04 Reset value 0x0020 This register can be accessed by h...

Page 321: ... 1 ALRMIF Alarm interrupt flag 0 Alarm event not detected 1 Alarm event detected An interrupt named RTC global interrupt will occur if the ALRMIE bit is set in RTC_INTEN And another interrupt named the RTC Alarm interrupt will occur if the EXTI 17 is enabled in interrupt mode 0 SCIF Second interrupt flag 0 Second event not detected 1 Second event detected An interrupt will occur if the SCIE bit is...

Page 322: ...ons 31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 RTC prescaler value low The frequency of SC_CLK is the RTCCLK frequency divided by PSC 19 0 1 17 4 5 RTC divider high register RTC_DIVH Address offset 0x10 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rese...

Page 323: ...ware when the RTC prescaler or RTC counter register updated 17 4 7 RTC counter high register RTC_CNTH Address offset 0x18 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 31 16 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CNT 31 16 RTC...

Page 324: ...rd 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALRM 31 16 w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 ALRM 31 16 RTC alarm value high 17 4 10 RTC alarm low register RTC_ALRML Address offset 0x24 Reset value 0xFFFF This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26...

Page 325: ...GD32F20x User Manual 325 15 0 ALRM 15 0 RTC alarm value low ...

Page 326: ...TI1 TIMER1_TRGO ITI2 TIMER2_TRGO ITI3 TIMER3_TRGO TIMER7 ITI0 TIMER0_TRGO ITI1 TIMER1_TRGO ITI2 TIMER3_TRGO ITI3 TIMER4_TRGO 2 TIMER1 ITI0 TIMER0_TRGO ITI1 refer to note 5 ITI2 TIMER2_TRGO ITI3 TIMER3_TRGO TIMER2 ITI0 TIMER0_TRGO ITI1 TIMER1_TRGO ITI2 TIMER4_TRGO ITI3 TIMER3_TRGO TIMER3 ITI0 TIMER0_TRGO ITI1 TIMER1_TRGO ITI2 TIMER2_TRGO ITI3 TIMER7_TRGO TIMER4 ITI0 TIMER1_TRGO ITI1 TIMER2_TRGO ITI...

Page 327: ...each other but they may be synchronized to provide a larger timer with their counters incrementing in unison 18 1 2 Characteristics Total channel num 4 Counter width 16 bit Source of counter clock is selectable internal clock internal trigger external input external trigger Multiple counter modes count up count down count up down Quadrature Decoder used to track motion and determine both rotation ...

Page 328: ...gle timer to initiate multiple timers Timer synchronization allows selected timers to start counting on the same clock cycle Timer Master Slave mode controller 18 1 3 Block diagram Figure 18 1 Advanced timer block diagram provides details of the internal configuration of ...

Page 329: ...t collector and controller APB BUS CK_TIMER CH0_IN CH1_IN CH2_IN CH3_IN CI0 ITI0 ITI1 ITI2 ITI3 ETI CAR Repeater Output Logic generation of outputs signals in compare PWM and mixed modes according to initialization complementary mode software output control deadtime insertion break input output mask and polarity control BKEN BRKIN CKM clock monitor CH0_O CH0_ON DMA controller TIMERx_TRGO DMA REQ A...

Page 330: ...lable value including 0x1 0x2 0x3 and 0x7 the prescaler is clocked by other clock sources selected by the TRGS 2 0 in the TIMERx_SMCFG register details as follows When the slave mode selection bits SMC 2 0 are set to 0x4 0x5 or 0x6 the internal clock TIMER_CK is the counter prescaler driving clock source Figure 18 2 Normal mode internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Relo...

Page 331: ...ock source the trigger controller including the edge detection circuitry will generate a clock pulse on each rising edge of ETI signal to provide clock to the counter prescaler Prescaler The prescaler can divide the timer clock TIMER_CK to a counter clock PSC_CLK by any factor between 1 and 65536 It is controlled by prescaler register TIMERx_PSC which can be changed on the go but is taken into acc...

Page 332: ...l be initialized to 0 and generates an update event If set the UPDIS bit in TIMERx_CTL0 register the update event is disabled When an update event occurs all the registers repetition counter auto reload register prescaler register are updated The following figures show some examples of the counter behavior for different clock prescaler factor when TIMERx_CAR 0x63 Figure 18 4 Up counter timechart P...

Page 333: ...in a count down direction Once the counter reaches to 0 the counter restarts to count again from the counter reload value If the repetition counter is set the update event will be generated after TIMERx_CREP 1 times of underflow Otherwise the update event is generated each time when underflows The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode ...

Page 334: ...mechart PSC 0 1 CEN CNT_CLK PSC_CLK CNT_REG 05 04 03 02 01 00 63 62 61 60 5F 5E 5C 5B Update event UPE Update interrupt flag UPIF CNT_REG 04 03 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set PSC 0 PSC 1 TIMER_CK 5A 00 01 02 63 62 61 CNT_CLK PSC_CLK ...

Page 335: ...oad value subtract 1 in the up counting direction and generates an underflow event when the counter counts to 1 in the down counting direction The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned mode The counting direction is updated by hardware automatically Setting the UPG bit in the TIMERx_SWEVG register will in...

Page 336: ...on Counter Repetition is used to generator update event or updates the timer registers only after a given number N 1 of cycles of the counter where N is CREP in TIMERx_CREP register The repetition counter is decremented at each counter overflow in up counting mode at each counter underflow in down counting mode or at each counter overflow and at each counter underflow in center aligned mode Settin...

Page 337: ... for center aligned counter CEN 03 02 01 00 01 02 62 63 62 61 01 00 Underflow Overflow TIMERx_CREP 0x0 TIMER_CK 01 02 62 63 62 61 UPIF TIMERx_CREP 0x1 01 00 01 02 62 63 62 61 UPIF UPIF TIMERx_CREP 0x2 CNT_CLK CNT_REG Figure 18 10 Repetition timechart for up counter CEN CNT_REG 60 61 62 63 00 01 62 63 00 01 62 63 Underflow Overflow TIMERx_CREP 0x0 TIMER_CK 00 01 62 63 00 01 UPIF TIMERx_CREP 0x1 62 ...

Page 338: ...s Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Input capture mode Capture mode allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input stage consists of a digital filter a channel polarity selection edge detection and a channel prescaler When a selected edge oc...

Page 339: ...g the IC_prescaler enables an effective capture event after a number of input events On the capture event CHxVAL will restore the value of Counter So the process can be divided to several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and requested signal quality configure compatible CHxCAPFLT Step2 Edge selection CHxP CHxNP in TIMERx_CHCTL2 Rising o...

Page 340: ...ogrammable position polarity duration and frequency When the counter matches the value in the CHxVAL register of an output compare channel the channel n output can be set cleared or toggled based on CHxCOMCTL When the counter reaches the value in the CHxVAL register the CHxIF bit is set and the channel n interrupt is generated if CHxIE 1 And the DMA request will be asserted if CHxDEN 1 So the proc...

Page 341: ...on the counter mode we can also divide PWM into EAPWM Edge aligned PWM and CAPWM Centre aligned PWM The EAPWM period is determined by TIMERx_CAR and duty cycle is determined by TIMERx_CHxCV Figure 18 14 EAPWM timechart shows the EAPWM output and interrupts waveform The CAPWM period is determined by 2 TIMERx_CAR and duty cycle is by 2 TIMERx_CHxCV Figure 18 15 CAPWM timechart shows the CAPWM output...

Page 342: ...used in the compare match output mode the OxCPRE signal Channel x Output prepare signal is defined by setting the CHxCOMCTL filed The OxCPRE signal has several types of output function These include keeping the original level by setting the CHxCOMCTL field to 0x00 set to 1 by setting the CHxCOMCTL field to 0x01 set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMC...

Page 343: ...date event occurs Outputs complementary Function of complementary is for a pair of CHx_O and CHx_ON Those two output signals cannot be active at the same time The TIMERx has 4 channels but only the first three channels have this function The complementary signals CHx_O and CHx_ON are controlled by a group of parameters the CHxEN and CHxNEN bits in the TIMERx_CHCTL2 register and the POEN ROS IOS IS...

Page 344: ... dead time delay that can be used for all channels expect for channel 3 The detail about the delay time refer to the register TIMERx_CCHP The dead time delay insertion ensures that no two complementary signals drive the active state at the same time When the channel x match TIMERx counter CHxVAL occurs OxCPRE will be toggled because under PWM0 mode At point A in the Figure 18 16 Complementary outp...

Page 345: ... The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register The break input polarity is setting by the BRKP bit in TIMERx_CCHP When a break occurs the POEN bit is cleared asynchronously the output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0 If IOS is 0 then the timer releases the output enable...

Page 346: ...r CI0 only CI1 only or both CI0 and CI1 the selection mode by setting the SMC 2 0 to 0x01 0x02 or 0x03 The mechanism for changing the counter direction is shown in the following table The quadrature decoder can be regarded as an external clock with a directional selection This means that the counter counts continuously in the interval between 0 and the counter reload value Therefore users must con...

Page 347: ...ee we need two timers First TIMER_in Advanced GeneralL0 TIMER should accept three Rotor Position signals from Motor Each of the 3 sensors provides a pulse that applied to an input capture pin can then be analyzed and both speed and position can be deduced By the internal connection such as TRGO ITIx TIMER_in and TIMER_out can be connected TIMER_out will generate PWM signal to control BLDC motor s ...

Page 348: ...te timers combination and wire connection we need to configure timers Some key settings include Enable XOR by setting TI0S then each change of input signal will make the CI0 toggle CH0VAL will record the value of counter at that moment Enable ITIx connected to commutation function directly by setting CCUC and CCSE Configuration PWM parameter based on your request Figure 18 20 Hall sensor is used t...

Page 349: ...0 TIMER_in under input capture mode Advanced TIMER_out under output compare mode PWM with Dead time Slave controller The TIMERx can be synchronized with a trigger in several modes including the restart mode the pause mode and the event mode which is selected by the SMC 2 0 in the TIMERx_SMCFG register The trigger input of these modes can be selected by the TRGS 2 0 in the TIMERx_SMCFG register ...

Page 350: ...n be used For the CIx configure Filter by CHxCAPFLT no prescaler can be used For the ETIF configure Filter by ETFC and Prescaler by ETPSC Exam1 Restart mode The counter can be clear and restart when a rising trigger input TRGS 2 0 3 b0 00 ITI0 is the selection For ITI0 no polarity selector can be used For the ITI0 no filter and prescaler can be used Figure 18 22 Restart mode TIMER_CK CEN CNT_REG 5...

Page 351: ...e which can be enabled by setting SPM in TIMERx_CTL0 When you set SPM the counter will be clear and stop when the next update event automatically In order to get pulse waveform you can set the TIMERx to PWM mode or compare by CHxCOMCTL Once the timer is set to operate in the single pulse mode it is not necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter...

Page 352: ...ich the OxCPRE signal will change to as the compare match event occurs without taking the comparison result into account The CHxCOMFEN bit is available only when the output channel is configured to operate in the PWM0 or PWM1 output mode and the trigger source is derived from the trigger signal Figure 18 25 Single pulse mode TIMERx_CHxCV 0x04 TIMERx_CAR 0x60 TIMER_CK CNT_CLK CEN CNT_REG 00 01 02 0...

Page 353: ...ER2_CTL1 register Then timer2 drives a periodic signal on each counter overflow 2 Configure the Timer2 period TIMER2_CAR registers 3 Select the Timer0 input trigger source from Timer2 TRGS 3 b010 in the TIMERx_SMCFG register 4 Configure Timer0 in external clock mode 0 SMC 3 b111 in TIMERx_SMCFG register 5 Start Timer0 by writing 1 in the CEN bit TIMER0_CTL0 register 6 Start Timer2 by writing 1 in ...

Page 354: ...Figure 18 27 Triggering TIMER0 with enable signal of TIMER2 TIMER_CK CNT_REG CNT_REG CEN 33 11 12 TRGIF 34 35 36 CEN 13 TIMER0 TIMER2 10 software clear 14 hardware set In this example we also can use update Event as trigger source instead of enable signal Refer to Figure 18 28 Triggering TIMER0 with update signal of TIMER2 Do as follow 1 Configure Timer2 in master mode and send its update event UP...

Page 355: ...frequencies are divided by 3 by the prescaler compared to CK_TIMER fCNT_CLK fPCLK 3 Timer0 s SMC is set as pause mode so Timer0 can be enabled disabled by Timer2 s enable disable signal Do as follow 1 Configure Timer2 in input master mode and its output enable signal as trigger output MMC 3 b001 in the TIMER2_CTL1 register 2 Configure Timer0 to get the input trigger from Timer2 TRGS 3 b010 in the ...

Page 356: ... the TIMER2_CTL1 register 2 Configure the Timer2 O0CPRE waveform TIMER2_CH0CTL register 3 Configure Timer0 to get the input trigger from Timer2 TRGS 3 b010 in the TIMERx_SMCFG register 4 Configure Timer0 in pause mode SMC 3 b101 in TIMERx_SMCFG register 5 Enable Timer0 by writing 1 in the CEN bit TIMER0_CTL0 register 6 Start Timer2 by writing 1 in the CEN bit TIMER2_CTL0 register Figure 18 30 Paus...

Page 357: ... b110 in the TIMER0_SMCFG register When a rising edge occurs on Timer2 s CI0 two timer s counters start counting synchronously on the internal clock and both TRGIF flags are set Figure 18 31 Triggering TIMER0 and TIMER2 with TIMER2 s CI0 input TIMER_CK CNT_REG CNT_REG CI0 00 01 CEN 02 03 00 01 02 03 CNT_CK TRGIF CEN TRGIF TIMER2 TIMER0 Timer DMA mode Timer s DMA mode is the function that configure...

Page 358: ...ore requests to DMA and DMA will access timer s registers DMATA 0x4 DMATA 0x8 DMATA 0xc at the next 3 accesses to TIMERx_DMATB In one word one time DMA internal interrupt event assert DMATC 1 times request will be send by TIMERx If one more time DMA request event coming TIMERx will repeat the process as above Timer debug mode When the Cortex M3 halted and the TIMERx_HOLD configuration bit in DBG_C...

Page 359: ...generators and the digital filters 00 fDTS fTIMER_CK 01 fDTS fTIMER_CK 2 10 fDTS fTIMER_CK 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified by the DIR bit 01 C...

Page 360: ...ates an overflow or underflow event The slave mode controller generates an update event 1 Only counter overflow underflow generates an update interrupt or DMA request 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 update event enable The update event is generate and the buffered registers are loaded with their preloaded values when one of the following e...

Page 361: ...it is reset CH0_ON is set low 1 When POEN bit is reset CH0_ON is set high This bit can be modified only when PROT 1 0 bits in TIMERx_CCHP register is 00 8 ISO0 Idle state of channel 0 output 0 When POEN bit is reset CH0_O is set low 1 When POEN bit is reset CH0_O is set high The CH0_O output changes after a dead time if CH0_ON is implemented This bit can be modified only when PROT 1 0 bits in TIME...

Page 362: ...mode controller selects the O2CPRE signal as TRGO 111 Compare In this mode the master mode controller selects the O3CPRE signal as TRGO 3 DMAS DMA request source selection 0 DMA request of channel x is sent when capture compare event occurs 1 DMA request of channel x is sent when update event occurs 2 CCUC Commutation control shadow register update control When the commutation control shadow enabl...

Page 363: ... or event mode But the TRGS bits must not be 3 b111 in this case The external clock input will be ETIF if external clock mode 0 and external clock mode 1 are enabled at the same time Note External clock mode 0 enable is in this register s SMC bit filed 13 12 ETPSC 1 0 External trigger prescaler The frequency of external trigger signal ETI can not exceed 1 4 of TIMER_CK frequency When the external ...

Page 364: ...10 Internal trigger input 2 ITI2 011 Internal trigger input 3 ITI3 100 CI0 edge flag CI0F_ED 101 channel 0 input Filtered output CI0FE0 110 channel 1 input Filtered output CI1FE1 111 External trigger input filter output ETIFP These bits must not be changed when slave mode is enabled 3 Reserved Must be kept at reset value 2 0 SMC 2 0 Slave mode control 000 Disable mode The slave mode is disabled Th...

Page 365: ...6 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRGDEN CMTDEN CH3DEN CH2DEN CH1DEN CH0DEN UPDEN BRKIE TRGIE CMTIE CH3IE CH2IE CH1IE CH0IE UPIE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 15 Reserved Must be kept at reset value 14 TRGDEN Trigger DMA request enable 0 disabled 1 enabled 13 CMTDEN Commutation DMA request enable 0 dis...

Page 366: ...bled 2 CH1IE Channel 1 capture compare interrupt enable 0 disabled 1 enabled 1 CH0IE Channel 0 capture compare interrupt enable 0 disabled 1 enabled 0 UPIE Update interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11...

Page 367: ...reak input is not active 0 No active level break has been detected 1 An active level has been detected 6 TRGIF Trigger interrupt flag This flag is set by hardware on trigger event and cleared by software When the slave mode controller is enabled in all modes but pause mode an active edge on trigger input generates a trigger event When the slave mode controller is enabled in pause mode both edges o...

Page 368: ...27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BRKG TRGG CMTG CH3G CH2G CH1G CH0G UPG w w w w w w w w Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 BRKG Break event generation This bit is set by software and cleared by hardware automatically When this bit is set the POEN bit is cleared and BRKIF flag is set related interrupt or DM...

Page 369: ...ode the current value of the counter is captured in TIMERx_CH0CV register and the CH0OF flag is set if the CH0IF flag was already high 0 No generate a channel 1 capture or compare event 1 Generate a channel 1 capture or compare event 0 UPG Update event generation This bit can be set by software and cleared by hardware automatically When this bit is set the counter is cleared if the center aligned ...

Page 370: ... only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register 7 CH0COMCEN Channel 0 output compare clear enable When this bit is set the O0CPRE signal is cleared when High level is detected on ETIF input 0 Channel 0 output compare clear disable 1 Channel 0 output compare clear enable 6 4 CH0COMCTL 2 0 Channel 0 compare output control This bit field controls the behavior...

Page 371: ...t cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH0MS bit filed is 00 2 CH0COMFEN Channel 0 output compare fast enable When this bit is set the effect of an event on the trigger in input on the capture compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode The output channel will treat an active edge on the trigger input as a compare mat...

Page 372: ...fSAMP fTIMER_CK N 2 0010 fSAMP fTIMER_CK N 4 0011 fSAMP fTIMER_CK N 8 0100 fSAMP fDTS 2 N 6 0101 fSAMP fDTS 2 N 8 0110 fSAMP fDTS 4 N 6 0111 fSAMP fDTS 4 N 8 1000 fSAMP fDTS 8 N 6 1001 fSAMP fDTS 8 N 8 1010 fSAMP fDTS 16 N 5 1011 fSAMP fDTS 16 N 6 1100 fSAMP fDTS 16 N 8 1101 fSAMP fDTS 32 N 5 1110 fSAMP fDTS 32 N 6 1111 fSAMP fDTS 32 N 8 3 2 CH0CAPPSC 1 0 Channel 0 input capture prescaler This bit...

Page 373: ...ption 9 8 CH3MS 1 0 Channel 3 mode selection This bit field specifies the direction of the channel and the input signal selection This bit field is writable only when the channel is not active CH3EN bit in TIMERx_CHCTL2 register is reset 00 Channel 3 is configured as output 01 Channel 3 is configured as input IS3 is connected to CI3FE3 10 Channel 3 is configured as input IS3 is connected to CI2FE3...

Page 374: ...de or when the result of the comparison changes This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH2MS bit filed is 00 COMPARE MODE 3 CH2COMSEN Channel 2 compare output shadow enable When this bit is set the shadow register of TIMERx_CH2CV register which updates at each update event will be enabled 0 Channel 2 output compare shadow disable 1 Channel 2 output co...

Page 375: ... 1 0 Channel 3 input capture prescaler Refer to CH0CAPPSC description 9 8 CH3MS 1 0 Channel 3 mode selection Same as Output compare mode 7 4 CH2CAPFLT 3 0 Channel 2 input capture filter control An event counter is used in the digital filter in which a transition on the output occurs after N input events This bit field specifies the frequency used to sample CI2 input signal and the length of the di...

Page 376: ...CH3EN CH2NP CH2NEN CH2P CH2EN CH1NP CH1NEN CH1P CH1EN CH0NP CH0NEN CH0P CH0EN rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 14 Reserved Must be kept at reset value 13 CH3P Channel 3 capture compare function polarity Refer to CH0P description 12 CH3EN Channel 3 capture compare function enable Refer to CH0EN description 11 CH2NP Channel 2 complementary output polarity Refer t...

Page 377: ...onfigured in output mode this bit specifies the output signal polarity 0 Channel 0 active high 1 Channel 0 active low When channel 0 is configured in input mode this bit specifies the CI0 signal polarity CH0NP CH0P will select the active trigger or capture polarity for CI0FE0 or CI1FE0 CH0NP 0 CH0P 0 CIxFE0 s rising edge is the active signal for capture or trigger operation in slave mode And CIxFE...

Page 378: ...s bit filed can change the value of the counter Prescaler register TIMERx_PSC Address offset 0x28 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 Prescaler value of the counter clock The ...

Page 379: ...by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CREP 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 CREP 7 0 Counter repetition value This bit filed specifies the update event generation rate Each time the repetition counter counting down to zero an update event is generated The update rate of the...

Page 380: ... 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH1VAL 15 0 Capture or compare value of channel1 When channel 1 is configured in input mode this bit filed indicates the counter value corresponding to the ...

Page 381: ...dress offset 0x40 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH3VAL 15 0 Capture or compare value of channel 3 When channel3 is configured in input mode this bit filed indicates the counte...

Page 382: ... can be not set by hardware 1 POEN can be set by hardware automatically at the next update event if the break input is not active This bit can be modified only when PROT 1 0 bit filed in TIMERx_CCHP register is 00 13 BRKP Break polarity This bit specifies the polarity of the BRKIN input signal 0 BRKIN input active low 1 BRKIN input active high 12 BRKEN Break enable This bit can be set to enable th...

Page 383: ...is configured in output mode and the ROS IOS bits in TIMERx_CCHP register are writing protected 11 PROT mode 2 In addition of the registers in PROT mode 1 the CHxCOMCTL CHxCOMSEN bits in TIMERx_CHCTL0 1 registers if the related channel is configured in output are writing protected This bit field can be written only once after the reset Once the TIMERx_CCHP register has been written this bit field ...

Page 384: ...ust access And then the second access to the TIMERx_DMATB you will access the address of start address 0x4 5 b0_0000 TIMERx_CTL0 5 b0_0001 TIMERx_CTL1 In a word Start Address TIMERx_CTL0 DMATA 4 DMA transfer buffer register TIMERx_DMATB Address offset 0x4C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11...

Page 385: ...GD32F20x User Manual 385 ...

Page 386: ...4 Counter width 16bit Source of count clock is selectable internal clock internal trigger external input external trigger Multiple counter modes count up count down count up down Quadrature decoder used to track motion and determine both rotation direction and position Hall sensor for 3 phase motor control Programmable prescaler 16 bit Factor can be changed on the go Each channel is user configura...

Page 387: ...ector Prescaler Filter TIMERx_CHxCV Register Interrupt Register set and update Interrupt collector and controller APB BUS CK_TIMER CH0_IN CH1_IN CH2_IN CH3_IN CI0 ITI0 ITI1 ITI2 ITI3 ETI CAR Output Logic generation of outputs signals in compare PWM and mixed modes according to initialization software output mask and polarity control CH0_O DMA controller TIMERx_TRGO Interrupt CH1_O CH2_O CH3_O Upda...

Page 388: ...prescaler is clocked by other clock sources selected by the TRGS 2 0 in the TIMERx_SMCFG register and described as follows When the slave mode selection bits SMC 2 0 are set to 0x4 0x5 or 0x6 the internal clock TIMER_CK is the counter prescaler driving clock source Figure 18 33 Normal mode internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event...

Page 389: ...he counter clock PSC_CLK by any factor between 1 and 65536 It is controlled through prescaler register TIMERx_PSC which can be changed on the go but be taken into account at the next update event Figure 18 34 Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK CEN PSC_CLK CNT_REG Reload Pulse Prescaler CNT Prescaler BUF F7 F8 F9 FA FB FC 01 02 03 0 1 0 1 0 1 0 1 0 1 0 1 PSC ...

Page 390: ...wing figures show some examples of the counter behavior for different clock prescaler factor when TIMERx_CAR 0x63 Figure 18 35 Up counter timechart PSC 0 1 CEN CNT_CLK PSC_CLK CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 05 06 07 Update event UPE Update interrupt flag UPIF CNT_REG 5F 60 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set PSC 0 PSC 1 TIMER_CK 08 63 62 6...

Page 391: ...direction Once the counter reaches to 0 the counter restarts to count again from the counter reload value If the repetition counter is set the update event was generated after the number TIMERx_CREP 1 of underflow Else the update event is generated at each counter underflow The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode When the update even...

Page 392: ... 62 61 CNT_CLK PSC_CLK Figure 18 38 Down counter timechart change TIMERx_CAR on the go TIMER_CK CEN CNT_CLK PSC_CLK CNT_REG 05 04 03 02 01 00 63 62 61 60 5F 5E 5D 5C Update event UPE Update interrupt flag UPIF Auto reload register 65 63 change CAR Vaule CNT_REG 05 04 03 02 01 00 63 01 00 65 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 change CAR Vaule 65 63 Auto reload sh...

Page 393: ...ng the UPG bit in the TIMERx_SWEVG register will initialize the counter value to 0 irrespective of whether the counter is counting up or down in the center align counting mode and generates an update event The UPIF bit in the TIMERx_INTF register can be set to 1 either when an underflow event or an overflow event occurs While the CHxIF bit is associated with the value of CAM in TIMERx_CTL0 The det...

Page 394: ...re inputs or compare match outputs Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Input capture mode Capture mode allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input stage consists of a digital filter a channel polarity selection edge detection and a channel ...

Page 395: ...e detected You can select one of them by CHxP One more selector is for the other channel and trig controlled by CHxMS Configuring the IC_prescaler enables an effective capture event after a number of input events On the capture event CHxVAL will restore the value of Counter So the process can be divided to several steps as below Step1 Filter Configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the in...

Page 396: ...e TIMERx_CH1CV can measure the PWM duty Output compare mode In Output Compare mode the TIMERx can generate timed pulses with programmable position polarity duration and frequency When the counter matches the value in the CHxVAL register of an output compare channel the channel n output can be set cleared or toggled based on CHxCOMCTL when the counter reaches the value in the CHxVAL register the CH...

Page 397: ...unter mode we have can also divide PWM into EAPWM Edge aligned PWM and CAPWM Centre aligned PWM The EAPWM period is determined by TIMERx_CAR and duty cycle is by TIMERx_CHxCV Figure 18 42 EAPWM timechart shows the EAPWM output and interrupts waveform The CAPWM period is determined by 2 TIMERx_CAR and duty cycle is determined by 2 TIMERx_CHxCV Figure 18 43 CAPWM timechart _Hlk454890020shows the CAP...

Page 398: ...utput reference signal When the TIMERx is used in the compare match output mode the OxCPRE signal Channel x Output prepare signal is defined by setting the CHxCOMCTL filed The OxCPRE signal has several types of output function These include keeping the original level by setting the CHxCOMCTL field to 0x00 set to 1 by setting the CHxCOMCTL field to 0x01 set to 0 by setting the CHxCOMCTL field to 0x...

Page 399: ...s Quadrature decoder The quadrature decoder function uses two quadrature inputs CI0 and CI1 derived from the TIMERx_CH0 and TIMERx_CH1 pins respectively to interact to generate the counter value The DIR bit is modified by hardware automatically during each input source transition The input source can be either CI0 only CI1 only or both CI0 and CI1 the selection made by setting the SMC 2 0 to 0x01 ...

Page 400: ...MERx_SMCFG register The trigger input of these modes can be selected by the TRGS 2 0 in the TIMERx_SMCFG register Table 18 6 Slave controller examples Mode Selection Source Selection Polarity Selection Filter and Prescaler LIST SMC 2 0 3 b100 restart mode 3 b101 pause mode 3 b110 event mode TRGS 2 0 000 ITI0 001 ITI1 010 ITI2 011 ITI3 100 CI0F_ED 101 CI0FE0 If you choose the CI0FE0 or CI1FE1 confi...

Page 401: ...e selection For ITI0 no polarity selector can be used For the ITI0 no filter and prescaler can be used Figure 18 46 Restart mode TIMER_CK CEN CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 00 01 02 UPIF ITI0 TRGIF Internal sync delay Exam2 Pause mode The counter can be paused when the trigger input is low TRGS 2 0 3 b 101 CI0FE0 is the selection TI0S 0 Non xor CH0NP 0 CH0P 0 no inverted Capture will be ...

Page 402: ...he CEN bit to 1 or a trigger from the trigger signals edge can generate a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 using software the counter will be stopped and its value held If the CEN bit is automatically cleared to 0 by a hardware update event the counter will be reinitialized In the...

Page 403: ...egister address then DMA will access the TIMERx_DMATB In fact register TIMERx_DMATB is only a buffer timer will map the TIMERx_DMATB to an internal register appointed by the field of DMATA in TIMERx_DMACFG If the field of DMATC in TIMERx_DMACFG is 0 1 transfer then the timer s DMA request is finished While if TIMERx_DMATC is not 0 such as 3 4 transfers then timer will send 3 more requests to DMA a...

Page 404: ...division ratio between the timer clock TIMER_CK and the dead time and sampling clock DTS which is used by the dead time generators and the digital filters 00 fDTS fTIMER_CK 01 fDTS fTIMER_CK 2 10 fDTS fTIMER_CK 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns ...

Page 405: ... 0 When enabled any of the following events generate an update interrupt or DMA request The UPG bit is set The counter generates an overflow or underflow event The slave mode controller generates an update event 1 When enabled only counter overflow underflow generates an update interrupt or DMA request 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 updat...

Page 406: ...er case the signal on TRGO is delayed compared to the actual reset 001 Enable This mode is useful to start several timers at the same time or to control a window in which a slave timer is enabled In this mode the master mode controller selects the counter enable signal TIMERx_EN as TRGO The counter enable signal is set when CEN control bit is set or the trigger input in pause mode is high There is...

Page 407: ...1 ETI is active at low level or falling edge 14 SMC1 Part of SMC for enable External clock mode1 In external clock mode 1 the counter is clocked by any active edge on the ETIF signal 0 External clock mode 1 disabled 1 External clock mode 1 enabled It is possible to simultaneously use external clock mode 1 with the restart mode pause mode or event mode But the TRGS bits must not be 3 b111 in this c...

Page 408: ...TS 32 N 6 1111 fSAMP fDTS 32 N 8 7 MSM Master slave mode This bit can be used to synchronize selected timers to begin counting at the same time The TRGI is used as the start event and through TRGO timers are connected together 0 Master slave mode disable 1 Master slave mode enable 6 4 TRGS 2 0 Trigger selection This bit field specifies which signal is selected as the trigger input which is used to...

Page 409: ...ables the counter when it is low 110 Event mode A rising edge of the trigger input enables the counter The counter cannot be disabled by the slave mode controller 111 External clock mode0 The counter counts on the rising edges of the selected trigger DMA and interrupt enable register TIMERx_DMAINTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 2...

Page 410: ...t be kept at reset value 4 CH3IE Channel 3 capture compare interrupt enable 0 disabled 1 enabled 3 CH2IE Channel 2 capture compare interrupt enable 0 disabled 1 enabled 2 CH1IE Channel 1 capture compare interrupt enable 0 disabled 1 enabled 1 CH0IE Channel 0 capture compare interrupt enable 0 disabled 1 enabled 0 UPIE Update interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF...

Page 411: ...reset value 6 TRGIF Trigger interrupt flag This flag is set by hardware on trigger event and cleared by software When the slave mode controller is enabled in all modes but pause mode an active edge on trigger input generates a trigger event When the slave mode controller is enabled in pause mode both edges on trigger input generates a trigger event 0 No trigger event occurred 1 Trigger interrupt o...

Page 412: ...et the TRGIF flag in TIMERx_STAT register is set related interrupt or DMA transfer can occur if enabled 0 No generate a trigger event 1 Generate a trigger event 5 Reserved Must be kept at reset value 4 CH3G Channel 3 s capture or compare event generation Refer to CH0G description 3 CH2G Channel 2 s capture or compare event generation Refer to CH0G description 2 CH1G Channel 1 s capture or compare ...

Page 413: ...OMCTL 2 0 CH1COM SEN CH1COM FEN CH1MS 1 0 CH0COM CEN CH0COMCTL 2 0 CH0COM SEN CH0COM FEN CH0MS 1 0 CH1CAPFLT 3 0 CH1CAPPSC 1 0 CH0CAPFLT 3 0 CH0CAPPSC 1 0 rw rw rw rw rw rw Output compare mode Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14 12 CH1COMCTL 2 0 Channel 1 compare output control Refe...

Page 414: ...en the counter matches the output compare register TIMERx_CH0CV 100 Force low O0CPRE is forced low level 101 Force high O0CPRE is forced high level 110 PWM mode0 When counting up O0CPRE is high as long as the counter is smaller than TIMERx_CH0CV otherwise it is low When counting down O0CPRE is low as long as the counter is larger than TIMERx_CH0CV otherwise it is high 111 PWM mode1 When counting u...

Page 415: ...HCTL2 register is reset 00 Channel 0 is configured as output 01 Channel 0 is configured as input IS0 is connected to CI0FE0 10 Channel 0 is configured as input IS0 is connected to CI1FE0 11 Channel 0 is configured as input IS0 is connected to ITS This mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register Input capture mode Bits Fields Descriptions...

Page 416: ...input edges 11 Capture is done every 8 channel input edges 1 0 CH0MS 1 0 Channel 0 mode selection Same as Output compare mode Channel control register 1 TIMERx_CHCTL1 Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3COM CEN CH3COMCTL 2 0 CH3COM SEN CH3COM FEN...

Page 417: ...the output reference signal O2CPRE which drives CH2_O and CH2_ON O2CPRE is active high while CH2_O and CH2_ON active level depends on CH2P and CH2NP bits 000 Frozen The O2CPRE signal keeps stable independent of the comparison between the output compare register TIMERx_CH2CV and the counter TIMERx_CNT 001 Set high on match O2CPRE signal is forced high when the counter matches the output compare reg...

Page 418: ...el independently from the result of the comparison 0 Channel 2 output quickly compare disable The minimum delay from an edge on the trigger input to activate CH2_O output is 5 clock cycles 1 Channel 2 output quickly compare enable The minimum delay from an edge on the trigger input to activate CH2_O output is 3 clock cycles 1 0 CH2MS 1 0 Channel 2 I O mode selection This bit field specifies the wo...

Page 419: ...6 N 8 1101 fSAMP fDTS 32 N 5 1110 fSAMP fDTS 32 N 6 1111 fSAMP fDTS 32 N 8 3 2 CH2CAPPSC 1 0 Channel 2 input capture prescaler This bit field specifies the factor of the prescaler on channel 2 input The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear 00 Prescaler disable capture is done on each channel input edge 01 Capture is done every 2 channel input edges 10 Capture is don...

Page 420: ...H1EN Channel 1 capture compare function enable Refer to CH0EN description 3 2 Reserved Must be kept at reset value 1 CH0P Channel 0 capture compare function polarity When channel 0 is configured in output mode this bit specifies the output signal polarity 0 Channel 0 active high 1 Channel 0 active low When channel 0 is configured in input mode this bit specifies the CI0 signal polarity 0 Channel 0...

Page 421: ...ister has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 Prescaler value of the counter clock The PSC clock is divided by PSC 1 to generate the counter clock The value of this bit filed will be loaded to the corresponding shadow...

Page 422: ...rved Must be kept at reset value 15 0 CH0VAL 15 0 Capture or compare value of channel0 When channel 0 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 0 is configured in output mode this bit filed contains value to be compared to the counter When the corresponding shadow register is enabled t...

Page 423: ...it 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH2VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH2VAL 15 0 Capture or compare value of channel 2 When channel 2 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When c...

Page 424: ...be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DMATC 4 0 Reserved DMATA 4 0 rw rw Bits Fields Descriptions 31 13 Reserved Must be kept at reset value 12 8 DMATC 4 0 DMA transfer count This filed is defined the number of DMA will access R W the register of TIMERx_DMATB 7 5 Reserved Must be kept at reset value 4 0 DM...

Page 425: ... 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMATB 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 DMATB 15 0 DMA transfer buffer When a read or write operation is assigned to this register the register located at the address range Start Addr Transfer Timer 4 will be accessed The transfer Timer is calculated by hardware and ranges from 0 to DMATC ...

Page 426: ...ized to provide a larger timer with their counters incrementing in unison 18 3 2 Characteristics Total channel num 2 Counter width 16bit Source of count clock is selectable internal clock internal trigger external input external trigger Multiple counter modes count up count down count up down Programmable prescaler 16 bit Factor can be changed on the go Each channel is user configurable Input capt...

Page 427: ... overview Clock selection The general level1 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC TIMERx_SMCFG bit 2 0 SMC 2 0 3 b000 Internal timer clock CK_TIMER which is from module RCU The default internal clock source is the CK_TIMER used to drive the counter prescaler when the slave mode is disabled SMC 2 0 3 b000 When the CEN is set...

Page 428: ...ck mode 1 External input pin source ETI The TIMER_CK driven counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin ETI This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1 The other way to select the ETI signal as the clock source is set the SMC 2 0 to 0x7 and the TRGS 2 0 to 0x7 respectively Note that the ETI signal ...

Page 429: ...he counter restarts to count once again from 0 The update event is generated at each counter overflow The counting direction bit DIR in the TIMERx_CTL1 register should be set to 0 for the up counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set t...

Page 430: ...IMER_CK 08 63 62 61 00 01 02 03 CNT_CLK PSC_CLK Figure 18 54 Up counter timechart change TIMERx_CAR on the go TIMER_CK CEN CNT_CLK PSC_CLK CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 05 06 07 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 change CAR Vaule CNT_REG 5E 5F 60 61 62 63 64 65 00 01 02 62 63 00 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 ch...

Page 431: ... update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to the counter reload value and generates an update event If set the UPDIS bit in TIMERx_CTL0 register the update event is disabled When an update event occurs all the registers repetition counter auto reload register prescaler register are updated The following figures show some examples of the ...

Page 432: ...oad value subtract 1 in the up counting direction and generates an underflow event when the counter counts to 1 in the down counting direction The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned mode The counting direction is updated by hardware automatically Setting the UPG bit in the TIMERx_SWEVG register will in...

Page 433: ...s The general level1 timer has two independent channels which can be used as capture inputs or compare match outputs Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Input capture mode Capture mode allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input stage consi...

Page 434: ... other channel and trig controlled by CHxMS Configuring the IC_prescaler enables an effective capture event after a number of input events On the capture event CHxVAL will restore the value of Counter So the process can be divided to several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and requested signal quality configure compatible CHxCAPFLT Ste...

Page 435: ...e TIMERx_CH1CV can measure the PWM duty Output compare mode In Output Compare mode the TIMERx can generate timed pulses with programmable position polarity duration and frequency When the counter matches the value in the CHxVAL register of an output compare channel the channel n output can be set cleared or toggled based on CHxCOMCTL when the counter reaches the value in the CHxVAL register the CH...

Page 436: ...e counter mode we can also divide PWM into EAPWM Edge aligned PWM and CAPWM Centre aligned PWM The EAPWM period is determined by TIMERx_CAR and duty cycle is determined by TIMERx_CHxCV Figure 18 60 EAPWM timechart shows the EAPWM output and interrupts waveform The CAPWM period is determined by 2 TIMERx_CAR and duty cycle is determined by 2 TIMERx_CHxCV Figure 18 61 CAPWM timechart shows the CAPWM ...

Page 437: ...xCPRE signal Channel x Output prepare signal is defined by setting the CHxCOMCTL filed The OxCPRE signal has several types of output function These include keeping the original level by setting the CHxCOMCTL field to 0x00 set to 1 by setting the CHxCOMCTL field to 0x01 set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value mat...

Page 438: ...al modes including the Restart mode the Pause mode and the Event mode which is selected by the SMC 2 0 in the TIMERx_SMCFG register The trigger input of these modes can be selected by the TRGS 2 0 in the TIMERx_SMCFG register Table 18 7 Slave controller examples Mode Selection Source Selection Polarity Selection Filter and Prescaler LIST SMC 2 0 3 b100 restart mode 3 b101 pause mode 3 b110 event m...

Page 439: ...aused when the trigger input is low TRGS 2 0 3 b10 1 CI0FE0 is the selection TI0S 0 Non xor CH0NP 0 CH0P 0 no inverted Capture will be sensitive to the rising edge only Filter is bypass in this example Figure 18 63 Pause mode TIMER_CK CEN CNT_REG 5E 5F 60 61 62 CI0 TRGIF CI0FE0 63 Exam3 Event mode The counter will start to count when a rising trigger input TRGS 2 0 3 b11 1 ETIF is the selection ET...

Page 440: ...n keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 using software the counter will be stopped and its value held If the CEN bit is automatically cleared to 0 by a hardware update event the counter will be reinitialized In the single pulse mode the trigger active edge which sets the CEN bit to 1 will enable the ...

Page 441: ...60 TIMER_CK CNT_CLK CEN CNT_REG 00 01 02 03 04 05 5F 60 00 O2CPRE CI3 Under SPM counter stop Timers interconnection Refer to Advanced timer TIMERx x 0 7 Timer debug mode When the Cortex M3 halted and the TIMERx_HOLD configuration bit in DBG_CTL2 register set to 1 the TIMERx counter stops ...

Page 442: ...fDTS fTIMER_CK 01 fDTS fTIMER_CK 2 10 fDTS fTIMER_CK 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified by the DIR bit 01 Center aligned and counting down assert...

Page 443: ...mode controller generates an update event 1 When enabled only counter overflow underflow generates an update interrupt or DMA request 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 update event enable The update event is generate and the buffered registers are loaded with their preloaded values when one of the following events occurs The UPG bit is set T...

Page 444: ...TI3 100 CI0 edge flag CI0F_ED 101 channel 0 input Filtered output CI0FE0 110 channel 1 input Filtered output CI1FE1 111 External trigger input filter output ETIFP These bits must not be changed when slave mode is enabled 3 Reserved Must be kept at reset value 2 0 SMC 2 0 Slave mode control 000 Disable mode The slave mode is disabled The prescaler is clocked directly by the internal clock TIMER_CK ...

Page 445: ...erved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRGIE Reserved CH1IE CH0IE UPIE rw rw rw rw Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 TRGIE Trigger interrupt enable 0 disabled 1 enabled 5 3 Reserved Must be kept at reset value 2 CH1IE Channel 1 capture compare interrupt enable 0 disabled 1 enabled 1 CH0IE Channel 0 capture compare interrupt enable 0 disabled 1 enabl...

Page 446: ...nd cleared by software When the slave mode controller is enabled in all modes but pause mode an active edge on trigger input generates a trigger event When the slave mode controller is enabled in pause mode both edges on trigger input generates a trigger event 0 No trigger event occurred 1 Trigger interrupt occurred 5 3 Reserved Must be kept at reset value 2 CH1IF Channel 1 s capture compare inter...

Page 447: ...ware in order to generate a capture or compare event in channel 0 it is automatically cleared by hardware When this bit is set the CH1IF flag is set the corresponding interrupt or DMA request is sent if enabled In addition if channel 1 is configured in input mode the current value of the counter is captured in TIMERx_CH0CV register and the CH0OF flag is set if the CH0IF flag was already high 0 No ...

Page 448: ...HCTL2 register is reset 00 Channel 1 is configured as output 01 Channel 1 is configured as input IS1 is connected to CI0FE1 10 Channel 1 is configured as input IS1 is connected to CI1FE1 11 Channel 1 is configured as input IS1 is connected to ITS This mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register 7 CH0COMCEN Channel 0 output compare clear ...

Page 449: ...update event will be enabled 0 Channel 0 output compare shadow disable 1 Channel 0 output compare shadow enable The PWM mode can be used without validating the shadow register only in single pulse mode SPM bit in TIMERx_CTL0 register is set This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH0MS bit filed is 00 2 CH0COMFEN Channel 0 output compare fast enable Wh...

Page 450: ...the frequency used to sample CI0 input signal and the length of the digital filter applied to CI0 0000 Filter disabled fSAMP fDTS N 1 0001 fSAMP fTIMER_CK N 2 0010 fSAMP fTIMER_CK N 4 0011 fSAMP fTIMER_CK N 8 0100 fSAMP fDTS 2 N 6 0101 fSAMP fDTS 2 N 8 0110 fSAMP fDTS 4 N 6 0111 fSAMP fDTS 4 N 8 1000 fSAMP fDTS 8 N 6 1001 fSAMP fDTS 8 N 8 1010 fSAMP fDTS 16 N 5 1011 fSAMP fDTS 16 N 6 1100 fSAMP fD...

Page 451: ... reset value When channel 0 is configured in input mode In conjunction with CH0P this bit is used to define the polarity of CI0 This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 or 10 2 Reserved Must be kept at reset value 1 CH0P Channel 0 capture compare function polarity When channel 0 is configured in output mode this bit specifies the output signal polarity 0 Ch...

Page 452: ...enabled Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CNT 15 0 This bit filed indicates the current counter value Writing to this bit filed can ch...

Page 453: ...L 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CARL 15 0 Counter auto reload value This bit filed specifies the auto reload value of the counter Channel 0 capture compare value register TIMERx_CH0CV Address offset 0x34 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 1...

Page 454: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH1VAL 15 0 Capture or compare value of channel1 When channel 1 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 1 is ...

Page 455: ...nt or time external events that drive other Timers 18 4 2 Characteristics Total channel num 1 Counter width 16bit Source of count clock is selectable internal clock internal trigger external input external trigger Multiple counter modes count up count down count up down Programmable prescaler 16 bit Factor can be changed on the go Each channel is user configurable Input capture mode output compare...

Page 456: ...initialization software output mask and polarity control CH0_O TIMERx_TRGO Interrupt Update Trigger Cap Com PSC TIMER_CK PSC_CLK 18 4 4 Function overview Clock selection The general level2 TIMER can only being clocked by the CK_TIMER Internal timer clock CK_TIMER which is from module RCU The general level2 TIMER has only one clock source which is the internal CK_TIMER used to drive the counter pre...

Page 457: ...ide the timer clock TIMER_CK to the counter clock PSC_CLK by any factor between 1 and 65536 It is controlled through prescaler register TIMERx_PSC which can be changed on the go but be taken into account at the next update event Figure 18 68 Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK CEN PSC_CLK CNT_REG Reload Pulse Prescaler CNT Prescaler BUF F7 F8 F9 FA FB FC 01 0...

Page 458: ...e counter value will be initialized to 0 and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an update event occurs all the registers repetition counter auto reload register prescaler register are updated The following figures show some examples of the counter behavior for different clock prescaler factor when TIMERx_CAR 0x63 Figure 18 69...

Page 459: ...s defined in the TIMERx_CAR register to 0 in a count down direction Once the counter reaches to 0 the counter restarts to count again from the counter reload value If the repetition counter is set the update event will be generated after TIMERx_CREP 1 times of underflow Otherwise the update event is generated each time when underflows The counting direction bit DIR in the TIMERx_CTL0 register shou...

Page 460: ...IMERx_CAR 0x63 Figure 18 71 Down counter timechart PSC 0 1 CEN CNT_CLK PSC_CLK CNT_REG 05 04 03 02 01 00 63 62 61 60 5F 5E 5C 5B Update event UPE Update interrupt flag UPIF CNT_REG 04 03 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set PSC 0 PSC 1 TIMER_CK 5A 00 01 02 63 62 61 CNT_CLK PSC_CLK ...

Page 461: ...act 1 in the up counting direction and generates an underflow event when the counter counts to 1 in the down counting direction The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned mode The counting direction is updated by hardware automatically Setting the UPG bit in the TIMERx_SWEVG register will initialize the co...

Page 462: ...imer has only one independent channel which can be used as capture inputs or compare match outputs This channel is built around a channel capture compare register including an input stage channel controller and an output stage Input capture mode Capture mode allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input stage consists of a digital f...

Page 463: ...umber of input events On the capture event CHxVAL will restore the value of Counter So the process can be divided to several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and requested signal quality configure compatible CHxCAPFLT Step2 Edge selection CHxP CHxNP in TIMERx_CHCTL2 Rising or falling edge choose one by CHxP CHxNP Step3 Capture source se...

Page 464: ...ulses with programmable position polarity duration and frequency When the counter matches the value in the CHxVAL register of an output compare channel the channel n output can be set cleared or toggled based on CHxCOMCTL when the counter reaches the value in the CHxVAL register the CHxIF bit is set and the channel n interrupt is generated if CHxIE 1 So the process can be divided to several steps ...

Page 465: ...xCV register The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06 0x07 In these modes the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content With regard to a more detail description refer to the relative bit definition Another spe...

Page 466: ...GD32F20x User Manual 466 Timer debug mode When the Cortex M3 halted and the TIMERx_HOLD configuration bit in DBG_CTL2 register set to 1 the TIMERx counter stops ...

Page 467: ...y division ratio between the timer clock TIMER_CK and the dead time and sampling clock DTS which is used by the dead time generators and the digital filters 00 fDTS fTIMER_CK 01 fDTS fTIMER_CK 2 10 fDTS fTIMER_CK 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter align...

Page 468: ...te an update interrupt or DMA request The UPG bit is set The counter generates an overflow or underflow event The slave mode controller generates an update event 1 When enabled only counter overflow underflow generates an update interrupt or DMA request 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 update event enable The update event is generate and th...

Page 469: ...time or to control a window in which a slave timer is enabled In this mode the master mode controller selects the counter enable signal TIMERx_EN as TRGO The counter enable signal is set when CEN control bit is set or the trigger input in pause mode is high There is a delay between the trigger input in pause mode and the TRGO output except if the master slave mode is selected 010 Update In this mo...

Page 470: ...date interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH0OF Reserved CH0IF UPIF rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31 10 Reserved Must be kept at reset value 9 CH0OF Chann...

Page 471: ...26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH0G UPG w w Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CH0G Channel 0 s capture or compare event generation This bit is set by software in order to generate a capture or compare event in channel 0 it is automatically cleared by hardware When this bit is set the CH1IF flag is set the ...

Page 472: ... 001 Set the channel output O0CPRE signal is forced high when the counter matches the output compare register TIMERx_CH0CV 010 Clear the channel output O0CPRE signal is forced low when the counter matches the output compare register TIMERx_CH0CV 011 Toggle on match O0CPRE toggles when the counter matches the output compare register TIMERx_CH0CV 100 Force low O0CPRE is forced low level 101 Force hi...

Page 473: ...e The minimum delay from an edge on the trigger input to activate CH0_O output is 5 clock cycles 1 Channel 0 output quickly compare enable The minimum delay from an edge on the trigger input to activate CH0_O output is 3 clock cycles 1 0 CH0MS 1 0 Channel 0 I O mode selection This bit field specifies the work mode of the channel and the input signal selection This bit field is writable only when t...

Page 474: ...ne on each channel input edge 01 Capture is done every 2 channel input edges 10 Capture is done every 4 channel input edges 11 Capture is done every 8 channel input edges 1 0 CH0MS 1 0 Channel 0 mode selection Same as output compare mode Channel control register 2 TIMERx_CHCTL2 Address offset 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22...

Page 475: ... mode And CIxFE0 will not be inverted CH0NP 0 CH0P 1 CIxFE0 s falling edge is the active signal for capture or trigger operation in slave mode And CIxFE0 will be inverted CH0NP 1 CH0P 0 Reserved CH0NP 1 CH0P 1 CIxFE0 s falling and rising edge are both the active signal for capture or trigger operation in slave mode And CIxFE0 will be not inverted This bit cannot be modified when PROT 1 0 bit filed...

Page 476: ...served 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 Prescaler value of the counter clock The PSC clock is divided by PSC 1 to generate the counter clock The value of this bit filed will be loaded to the corresponding shadow register at every update event Counter auto reload register TIMERx_CAR Address offset 0x2...

Page 477: ...19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH0VAL 15 0 Capture or compare value of channel0 When channel 0 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 0 is configured in output mode th...

Page 478: ...le counter modes count up Programmable prescaler 16 bit Factor can be changed on the go Single pulse mode is supported Auto reload function Interrupt output or DMA request on update event 18 5 3 Block diagram Figure 18 76 Basic timer block diagram provides details on the internal configuration of the basic timer Figure 18 76 Basic timer block diagram PSC Trigger processor Trigger Selector Counter ...

Page 479: ...t the CK_TIMER will be divided by PSC value to generate PSC_CLK Figure 18 77 Normal mode internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 05 06 07 Update event UPE Prescaler The prescaler can divide the timer clock TIMER_CK to the counter clock PSC_CLK by any factor between 1 and 65536 It is controlled thro...

Page 480: ...n Once the counter reaches the counter reload value the counter restarts to count once again from 0 The update event is generated at each counter overflow When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If set the UPDIS bit in TIMERx_CTL0 register the update event is disabled When an update event occu...

Page 481: ...IMER_CK 08 63 62 61 00 01 02 03 CNT_CLK PSC_CLK Figure 18 80 Up counter timechart change TIMERx_CAR on the go TIMER_CK CEN CNT_CLK PSC_CLK CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 05 06 07 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 change CAR Vaule CNT_REG 5E 5F 60 61 62 63 64 65 00 01 02 62 63 00 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 ch...

Page 482: ...GD32F20x User Manual 482 Timer debug mode When the Cortex M3 halted and the TIMERx_HOLD configuration bit in DBG_CTL2 register set to 1 the TIMERx counter stops ...

Page 483: ...ue 3 SPM Single pulse mode 0 Counter continues after update event 1 The CEN is cleared by hardware and the counter stops at next update event 2 UPS Update source This bit is used to select the update event sources by software 0 When enabled any of the following events generate an update interrupt or DMA request The UPG bit is set The counter generates an overflow or underflow event The slave mode ...

Page 484: ... Reserved Must be kept at reset value 6 4 MMC 2 0 Master mode control These bits control the selection of TRGO signal which is sent in master mode to slave timers for synchronization function 000 Reset When the UPG bit in the TIMERx_SWEVG register is set or a reset is generated by the slave mode controller a TRGO pulse occurs And in the latter case the signal on TRGO is delayed compared to the act...

Page 485: ...DMA request enable 0 disabled 1 enabled 7 1 Reserved Must be kept at reset value 0 UPIE Update interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UPIF rc_w0 Bits Fields Descriptions...

Page 486: ...automatically When this bit is set the counter is cleared The prescaler counter is cleared at the same time 0 No update event occurred 1 Generate an update event Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits Fields...

Page 487: ...y PSC 1 to generate the counter clock The value of this bit filed will be loaded to the corresponding shadow register at every update event Counter auto reload register TIMERx_CAR Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fields Descript...

Page 488: ...ports multiprocessor communication mode and hardware flow control protocol CTS RTS The data frame can be transferred from LSB or MSB bit The polarity of the data bits and the TX RX pins can be configured flexibly ALL USARTs support DMA function for high speed data communication 19 2 Characteristics NRZ standard format Asynchronous full duplex communication Programmable baud rate generator Divided ...

Page 489: ...d IDLEF Flags for smartcard block mode end of block EBF and receiver timeout RTF Interrupt occurs at these events when the corresponding interrupt enable bits are set While USART0 1 2 5 is fully implemented UART3 4 6 7 is only partially implemented with the following features not supported Smartcard mode Synchronous mode Hardware flow control protocol CTS RTS Configurable data polarity 19 3 Functi...

Page 490: ...by the WL bit in the USART_CTL0 register The last data bit can be used as parity check bit by setting the PCEN bit of in USART_CTL0 register When the WL bit is reset the parity bit is the 7th bit When the WL bit is set the parity bit is the 8th bit The method of calculating the parity bit is selected by the PM bit in USART_CTL0 register Figure 19 2 USART character frame 8 bits data and 1 stop bit ...

Page 491: ...nable bit TEN in USART_CTL0 register is set when the transmit data buffer is not empty the transmitter shifts out the transmit data frame through the TX pin The polarity of the TX pin can be configured by the TINV bit in the USART_CTL3 register Clock pulses can be output through the CK pin After the TEN bit is set an idle frame will be sent The TEN bit should not be reset while the transmission is...

Page 492: ... data1 to USART_DATA by DMA or software Write data2 to USART_DATA by DMA or software set by hardware set by hardware USART_DATA TBE TEN TX pin idle frame frame0 frame1 frame2 data0 data1 data2 set by hardware cleared by software TC It is necessary to wait for the TC bit asserted before disabling the USART or entering the power saving mode This bit can be cleared by a software sequence reading the ...

Page 493: ...R status will be generated for the frame An interrupt is generated if the receive DMA is enabled and the ERRIE bit in USART_CTL2 register is set Figure 19 4 Oversampling method of a receive frame bit 0 2 4 6 8 10 12 14 1 3 5 7 9 11 13 15 one frame bit sample bits oversampling 16 mode RX pin If the parity check function is enabled by setting the PCEN bit in the USART_CTL0 register the receiver calc...

Page 494: ...on Set the address of USART_DATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA interrupt enable priority etc Clear the TC bit in USART_STAT0 Enable the DMA channel for USART Wait the TC bit to be set After all of the data frames are transmitted the TC bit in USART_S...

Page 495: ...the DMA channel for USART When the number of the data received by USART reaches the DMA transfer number an end of transfer interrupt can be generated in the DMA module 19 3 6 Hardware flow control The hardware flow control function is realized by the nCTS and nRTS pins The RTS flow control is enabled by writing 1 to the RTSEN bit in USART_CTL2 and the CTS flow control is enabled by writing 1 to th...

Page 496: ... the CTS flow control is enabled the CTSF bit in USART_STAT0 is set when the nCTS pin toggles An interrupt is generated if the CTSIE bit in USART_CTL2 is set 19 3 7 Multi processor communication In multiprocessor communication several USARTs are connected as a network It will be a big burden for a device to monitor all of the messages on the RX pin To reduce the burden of a device software can put...

Page 497: ...ts in USART_CTL2 should be reset in LIN mode When transmitting a normal data frame the transmission procedure is the same as the normal USART mode The data bits length can only be 8 When the SBKCMD bit in USART_CTL0 is set the USART transmits continuous 13 0 bits following by 1 stop bit The break detection function is totally independent from the normal USART receiver So a break frame can be detec...

Page 498: ...g the start bit and stop bit transmission The CLEN bit in USART_CTL1 can be used to determine whether the clock is output or not during the last address flag bit transmission The CPH bit in USART_CTL1 can be used to determine whether data is captured on the first or the second clock edge The CPL bit in USART_CTL1 can be used to configure the clock polarity in the USART synchronous idle state The C...

Page 499: ...d transmitted to the infrared LED through the TX pin The SIR receive decoder receives the modulated signal from the infrared LED through the RX pin and puts the demodulated data frame to the USART receiver The baud rate should not be larger than 115200 for the encoder Figure 19 13 IrDA SIR ENDEC module Normal USART Transmit Encoder Receive Decoder SIR MODULE TX RX TX pin RX pin IREN 1 0 0 1 Infrar...

Page 500: ...CTL2 The LMEN CKEN bits in USART_CTL1 and SCEN IREN bits in USART_CTL2 should be reset in half duplex communication mode In the half duplex mode the receive line is internally connected to the TX pin and the RX pin is no longer used The TX pin should be configured as output open drain mode The software should make sure the transmission and reception process never conflict each other 19 3 12 Smartc...

Page 501: ...y pulling down the TX pin during the last 1 bit time of the stop bits The USART can automatically resend data according to the protocol by SCRTNUM times An interframe gap of 2 5 bits time will be inserted before the start of a resented frame At the end of the last repeated character the TC bit is set immediately without gardtime The USART will stop transmitting and assert the framing error status ...

Page 502: ...ck prologue field The block length counter counts up from 0 to the maximum value of BL 4 The end of the block status EBF bit in USART_STAT1 is set after the block length counter reaches the maximum value An interrupt is generated if the EBIE bit in USART_CTL3 is set The RTF bit may be set in case of an error in the block length If DMA is used for reception this register field must be programmed to...

Page 503: ...3 RTIE End of Block EBF USART_CTL3 EBIE Reception Errors Noise flag overrun error framing error in DMA reception NERR or ORERR or FERR USART_CTL2 ERRIE All of the interrupt events are logically ORed together before being sent to the interrupt controller so the USART can only generate a single interrupt request to the controller at any given time Software can service multiple interrupt events in a ...

Page 504: ...eserved Must be kept the reset value 9 CTSF CTS change flag If CTSEN bit in USART_CTL2 is set this bit is set by hardware when the nCTS input toggles An interrupt occurs if the CTSIE bit in USART_CTL2 is set Software can clear this bit by writing 0 to it 0 The status of the nCTS line does not change 1 The status of the nCTS line has changed This bit is not available for UART3 4 6 7 8 LBDF LIN brea...

Page 505: ...Read data buffer is empty 1 Read data buffer is not empty 4 IDLEF IDLE frame detected flag This bit is set when the RX pin has been detected in idle state for a frame time An interrupt occurs if the IDLEIE bit in USART_CTL0 is set Software can clear this bit by reading the USART_STAT0 and USART_DATA registers one by one 0 The USART module does not detect an IDLE frame 1 The USART module has detect...

Page 506: ...er 0 The USART does not detect a parity error 1 The USART has detected a parity error 19 4 2 Data register USART_DATA Offset 0x04 Reset value Undefined This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DATA 8 0 rw Bits Fields Descriptions 31 9 Reserved Must be kept the reset value 8 0 DATA 8 0 Tra...

Page 507: ...s to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UEN WL WM PCEN PM PERRIE TBEIE TCIE RBNEIE IDLEIE TEN REN RWU SBKCMD rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 14 Reserved Must be kept the reset value 13 UEN USART enable 0 USART disabled 1 USART enabled 12 WL Word length 0 8 Data bits...

Page 508: ...ete interrupt is enabled 5 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable If this bit is set an interrupt occurs when the RBNE bit or the ORERR bit in USART_STAT0 is set 0 Read data register not empty interrupt and overrun error interrupt disabled 1 Read data register not empty interrupt and overrun error interrupt enabled 4 IDLEIE IDLE line detected interrupt enabl...

Page 509: ...16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LMEN STB 1 0 CKEN CPL CPH CLEN Reserved LBDIE LBLEN Reserved ADDR 3 0 rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 15 Reserved Must be kept the reset value 14 LMEN LIN mode enable 0 LIN mode disabled 1 LIN mode enabled This bit field cannot be written when the USART is enabled UEN 1 13 12 STB 1 0 STOP bits length 00 1 Stop bit 01...

Page 510: ...8 bit frame and 9 CK pulses for a 9 bit frame This bit field cannot be written when the USART is enabled UEN 1 This bit is reserved for UART3 4 6 7 7 Reserved Must be kept the reset value 6 LBDIE LIN break detected interrupt enable If this bit is set an interrupt occurs when the LBDF bit in USART_STAT0 is set 0 LIN break detected interrupt is disabled 1 LIN break detected interrupt is enabled 5 LB...

Page 511: ...r UART3 4 6 7 8 RTSEN RTS enable This bit enables the RTS hardware flow control function 0 RTS hardware flow control disabled 1 RTS hardware flow control enabled This bit field cannot be written when the USART is enabled UEN 1 This bit is reserved for UART3 4 6 7 7 DENT DMA request enable for transmission 0 DMA request is disabled for transmission 1 DMA request is enabled for transmission 6 DENR D...

Page 512: ...s the IrDA mode of USART 0 IrDA disabled 1 IrDA enabled This bit field cannot be written when the USART is enabled UEN 1 0 ERRIE Error interrupt enable When DMA request for reception is enabled DENR 1 if this bit is set an interrupt occurs when any one of the FERR ORERR and NERR bits in USART_STAT0 is set 0 Error interrupt disabled 1 Error interrupt enabled 19 4 7 Guard time and prescaler register...

Page 513: ...ide the peripheral clock APB1 APB2 to generate the smartcard clock CK The actual division factor is twice as the PSC 4 0 value 00000 Reserved never program this value 00001 divides by 2 00010 divides by 4 11111 divides by 62 The PSC 7 5 bits are reserved in smartcard mode This bit field cannot be written when the USART is enabled UEN 1 19 4 8 Control register 3 USART_CTL3 Address offset 0x80 Reset...

Page 514: ...errupt enable bit of end of block event If this bit is set an interrupt occurs when the EBF bit in USART_STAT1 is set 0 End of block interrupt is enabled 1 End of block interrupt is disabled 4 RTIE Interrupt enable bit of receive timeout event If this bit is set an interrupt occurs when the RTF bit in USART_STAT1 is set 0 Receive timeout interrupt is enabled 1 Receive timeout interrupt is disabled...

Page 515: ...martcard mode In other modes when REN 0 receiver disabled or when the EBF bit of USART_STAT1 is written to 0 the block length counter is reset 23 0 RT 23 0 Receiver timeout threshold These bits are used to specify receiver timeout value in terms of number of baud clocks If Smartcard mode is not enabled the RTF bit of USART_STAT1 is set if no new start bit is detected longer than RT bits time after...

Page 516: ... This bit is set when the number of received bytes from the start of the block including the prologue is equal or greater than BLEN 4 An interrupt occurs if the EBIE bit in USART_CTL3 is set Software can clear this bit by writing 0 to it 0 End of block event not occurs 1 End of block event has occurred 11 RTF Receiver timeout flag This bit is set when the RX pin is in idle state for longer than RT...

Page 517: ... interface provides DMA mode for users to reduce CPU overload 20 2 Characteristics Parallel bus to I2C bus protocol converter and interface Both master and slave functions with the same interface Bi directional data transfer between master and slave Supports 7 bit and 10 bit addressing and general call addressing Multi master capability Supports standard mode up to 100 kHz and fast mode up to 400 ...

Page 518: ...er generates clock signals and terminates a transfer Slave the device addressed by a master Multi master more than one master can attempt to control the bus at the same time without corrupting the message Synchronization procedure to synchronize the clock signals of two or more devices Arbitration procedure to ensure that if more than one master tries to control the bus simultaneously only one is ...

Page 519: ...he HIGH period of the clock The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW see Figure 20 2 Data validation One clock pulse is generated for each data bit transferred Figure 20 2 Data validation 20 3 3 START and STOP condition All transactions begin with a START S and are terminated by a STOP P see Figure 20 3 START and STOP condition A HIGH to L...

Page 520: ...ait count 20 3 5 Arbitration Arbitration like synchronization is part of the protocol where more than one master is used in the system Slaves are not involved in the arbitration procedure A master may start a transfer only if the bus is free Two masters may generate a START condition within the minimum hold time of the START condition which results in a valid START condition on the bus Arbitration...

Page 521: ...data transfer N 1 bytes From master to slave From slave to master W 0 DATA0 ACK DATAN NACK Figure 20 7 I2C communication flow with 10 bit address Master Transmit Start Slave address byte2 W 0 ACK DATA0 ACK DATAN ACK NACK Stop data transfer N 1 bytes From master to slave From slave to master Slave address byte1 hreader ACK 1 1 1 1 0 x x write Figure 20 8 I2C communication flow with 10 bit address M...

Page 522: ...r should then send a repeated START Sr condition followed by a header to the I2C bus The slave sets ADDSEND bit again after it detects the repeated START Sr condition and the following header Software needs to clear the ADDSEND bit again by reading I2C_STAT0 and then I2C_STAT1 3 Now I2C enters data transmission stage and hardware sets TBE bit because both the shift register and data register I2C_D...

Page 523: ...GD32F20x User Manual 523 clears AERR bit by writing 0 to it ...

Page 524: ...AERR I2C Line State Hardware Action Software Flow Master sends Header Slave sends Acknowledge Programming model in slave receiving mode As is shown in Figure 20 10 Programming model for slave receiving the following software procedure should be followed if users wish to make reception in slave receiver mode 1 First of all software should enable I2C peripheral clock as well as configure clock relat...

Page 525: ... N Slave sends Acknowledge Master generates STOP condition Set ADDSEND 2 Clear ADDSEND Set RBNE Set STPDET 4 Read DATA x Set RBNE 3 Read DATA 1 5 Read DATA N 6 Clear STPDET I2C Line State Hardware Action Software Flow Set RBNE 1 Software initialization Programming model in master transmitting mode As it shows in Figure 20 11 Programming model for master transmitting the following software procedur...

Page 526: ...mpty Software now write the first byte data to I2C_DATA register but the TBE is not cleared because the write byte in I2C_DATA is moved to internal shift register immediately The I2C begins to transmit data to I2C bus as soon as shift register is not empty 6 During the first byte s transmission software can write the second byte to I2C_DATA and this time TBE is cleared because neither I2C_DATA nor...

Page 527: ...E 9 Set STOP I2C Line State Hardware Action Software Flow 2 Set START Set SBSEND SCL stretched by master 3 Clear SBSEND SCL stretched by master SCL stretched by master Programming model in master receiving mode In master receiving mode a master is responsible for generating NACK for the last byte reception and then sending STOP condition on I2C bus So special attention should be paid to ensure the...

Page 528: ...RT bit again to generate a repeated START condition on I2C bus and SBSEND is set after the repeated START is sent Software should clear the SBSEND bit by reading I2C_STAT0 and writing header to I2C_DATA Then the header is sent out to I2C bus and ADDSEND is set again Software should again clear ADDSEND by reading I2C_STAT0 and then I2C_STAT1 5 As soon as the first byte is received RBNE is set by ha...

Page 529: ...ched by master 4 Set START Master generates repeated START condition Set SBSEND 4 Clear SBSEND SCL stretched by master Master sends Header Slave sends Acknowledge Set ADDSEND 4 Clear ADDSEND SCL stretched by master 6 Read DATA N 1 7 Clear ACKEN Set STOP Solution B 1 First of all software should enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correc...

Page 530: ...oftware can read a byte from I2C_DATA until the master receives N 3 bytes As shown in Figure 20 13 Programming model for master receiving using solution B the N 2 byte is not read out by software so after the N 1 byte is received both BTC and RBNE are asserted The bus is stretched by master to prevent the reception of the last byte Then software should clear ACKEN bit 7 Software reads out N 2 byte...

Page 531: ...3 Set RBNE 5 Read DATA 1 Slave sends DATA N 1 Master sends Acknowledge Set RBNE 8 Read DATA N 2 I2C Line State Hardware Action Software Flow 2 Set START Set SBSEND SCL stretched by master 3 Clear SBSEND SCL stretched by master 4 Set START Master generates repeated START condition Set SBSEND 4 Clear SBSEND SCL stretched by master Master sends Header Slave sends Acknowledge Set ADDSEND 4 Clear ADDSE...

Page 532: ...is a CRC 8 calculator in I2C block to perform Packet Error Checking for I2C data The polynomial of the CRC is x8 x2 x 1 which is compatible with the SMBus protocol If enabled by setting PECEN bit the PEC will calculate all the data including address transmitted through I2C I2C is able to send out the PEC value after the last data byte or check the received PEC value with its calculated PEC using t...

Page 533: ...s no limit in the I2C bus protocol as to how long this delay can be whereas for a SMBus system it would be limited to 35ms SMBus protocol just assumes that if something takes too long then it means that there is a problem on the bus and that all devices must reset in order to clear this mode Slave devices are not allowed to hold the clock low too long Packet error checking SMBus 2 0 and 1 1 allow ...

Page 534: ...e asserted from these flags by setting some register bits refer to I2C register for detail Table 20 2 Event status flags Event Flag Name Description SBSEND START condition sent master ADDSEND Address sent or received ADD10SEND Header of 10 bit address sent STPDET STOP condition detected BTC Byte transmission completed TBE I2C_DATA is empty when transmitting RBNE I2C_DATA is not empty when receivin...

Page 535: ...t be kept the reset value 13 SALT SMBus Alert Issue alert through SMBA pin Software can set and clear this bit and hardware can clear this bit 0 Don t issue alert through SMBA pin 1 Issue alert through SMBA pin 12 PECTRANS PEC Transfer Software set and clear this bit while hardware clears this bit when PEC is transferred or START STOP condition detectedor I2CEN 0 0 Don t transfer PEC value 1 Trans...

Page 536: ...condition detected or I2CEN 0 0 START will not be sent 1 START will be sent 7 DISSTRC Whether to stretch SCL low when data is not ready in slave mode This bit is set and cleared by software 0 SCL Stretching is enabled 1 SCL Stretching is disabled 6 GCEN Whether or not to response to a General Call 0x00 0 Slave won t response to a General Call 1 Slave will response to a General Call 5 PECEN PEC Cal...

Page 537: ... 1 if EVIE 1 9 EVIE Event interrupt enable 0 Event interrupt disabled 1 Event interrupt enabled means that interrupt will be generated when SBSEND ADDSEND ADD10SEND STPDET or BTC flag asserted or TBE 1 or RBNE 1 if BUFIE 1 8 ERRIE Error interrupt enable 0 Error interrupt disabled 1 Error interrupt enabled means that interrupt will be generated when BERR LOSTARB AERR OUERR PECERR SMBTO or SMBALT fl...

Page 538: ...t Address 14 10 Reserved Must be kept the reset value 9 8 ADDRESS 9 8 Highest two bits of a 10 bit address 7 1 ADDRESS 7 1 7 bit address or bits 7 1 of a 10 bit address 0 ADDRESS0 Bit 0 of a 10 bit address 20 4 4 Slave address register 1 I2C_SADDR1 Address offset 0x0C Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ...

Page 539: ...OSTARB BERR TBE RBNE Reserved STPDET ADD10SEND BTC ADDSEND SBSEND rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 r r r r r r r Bits Fields Descriptions 15 SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0 0 SMBA pin not pulled down device mode or no Alert detected host mode 1 SMBA pin pulled down device mode or Alert detected host mode 14 SMBTO Timeout signal in SMBus mode ...

Page 540: ...ardware and cleared by writing 0 0 No bus error 1 A bus error detected 7 TBE I2C_DATA is Empty during transmitting This bit is set by hardware after it moves a byte from I2C_DATA to shift register and cleared by writing a byte to I2C_DATA If both the shift register and I2C_DATA are empty writing I2C_DATA won t clear TBE refer to Programming Model for detail 0 I2C_DATA is not empty 1 I2C_DATA is em...

Page 541: ...de or received and matches in slave mode This bit is set by hardware and cleared by reading I2C_STAT0 and reading I2C_STAT1 0 No address sent or received 1 Address sent out in master mode or a matched address is received in salve mode 0 SBSEND START condition sent out in master mode This bit is set by hardware and cleared by reading I2C_STAT0 and writing I2C_DATA 0 No START condition sent 1 START ...

Page 542: ...ress 00h received 1 General call address 00h received 3 Reserved Must be kept the reset value 2 TRS Whether the I2C is a transmitter or a receiver This bit is cleared by hardware after a STOP or a START condition or I2CEN 0 or LOSTARB 1 0 Receiver 1 Transmitter 1 I2CBSY Busy flag This bit is cleared by hardware after a STOP condition 0 No I2C communication 1 I2C communication active 0 MASTER A fla...

Page 543: ...ed mode if DTCY 0 Thigh CLKC TPCLK1 Tlow 2 CLKC TPCLK1 In fast speed mode if DTCY 1 Thigh 9 CLKC TPCLK1 Tlow 16 CLKC TPCLK1 20 4 9 Rise time register I2C_RT Address offset 0x20 Reset value 0x0002 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RISETIME 5 0 rw Bits Fields Descriptions 15 6 Reserved Must be kept the reset value 5 0 RISE...

Page 544: ...ansmission and reception 21 2 Characteristics 21 2 1 SPI characteristics Master or slave operation with full duplex or simplex mode Separate transmit and receive buffer 16 bits wide Data frame size can be 8 or 16 bits Bit order can be LSB first or MSB first Software and hardware NSS management Hardware CRC calculation transmission and checking Transmission and reception using DMA Quad SPI configur...

Page 545: ...iguration Not Quad SPI Mode Table 21 1 SPI signal description Pin Name Direction Description SCK I O Master SPI Clock Output Slave SPI Clock Input MISO I O Master Data reception line Slave Data transmission line Master with Bidirectional mode Not used Slave with Bidirectional mode Data transmission and reception Line MOSI I O Master Data transmission line Slave Data reception line Master with Bidi...

Page 546: ...3_DRV bit in SPI_QCTL register The SPI is connected to external devices through 6 pins in Quad SPI mode Table 21 2 Quad SPI signal description Pin Name Direction Description SCK O SPI Clock Output MOSI I O Transmission or Reception Data 0 line MISO I O Transmission or Reception Data 1 line IO2 I O Transmission or Reception Data 2 line IO3 I O Transmission or Reception Data 3 line NSS O NSS output ...

Page 547: ...e length of data is configured by the FF16 bit in the SPI_CTL0 register Data length is 16 bits if FF16 1 otherwise is 8 bits The data frame length is fixed to 8 bits in Quad SPI mode Data order is configured by LF bit in SPI_CTL0 register and SPI will first send the LSB if LF 1 or the MSB if LF 0 21 5 2 NSS function Slave Mode When slave mode is configured MSTMOD 0 SPI gets NSS level from NSS pin ...

Page 548: ... NSS pin to realize more flexible NSS 21 5 3 SPI operation modes Table 21 3 SPI operation modes Mode Description Register Configuration Data Pin Usage MFD Master Full Duplex MSTMOD 1 RO 0 BDEN 0 BDOEN Don t care MOSI Transmission MISO Reception MTU Master Transmission with unidirectional connection MSTMOD 1 RO 0 BDEN 0 BDOEN Don t care MOSI Transmission MISO Not used MRU Master Reception with unid...

Page 549: ...O Not used STB Slave Transmission with bidirectional connection MSTMOD 0 RO 0 BDEN 1 BDOEN 1 MOSI Not used MISO Transmission SRB Slave Reception with bidirectional connection MSTMOD 0 RO 0 BDEN 1 BDOEN 0 MOSI Not used MISO Reception Figure 21 4 A typical Full duplex connection Master MFD MISO MOSI SCK NSS Slave SFD MISO MOSI SCK NSS Figure 21 5 A typical simplex connection Master Receive Slave Tra...

Page 550: ... SPI_CTL0 register to generate SCK with desired baud rate otherwise ignore this step 2 Program data format FF16 bit in the SPI_CTL0 register 3 Program the clock timing register CKPL and CKPH bits in the SPI_CTL0 register 4 Program the frame format LF bit in the SPI_CTL0 register 5 Program the NSS mode SWNSSEN and NSSDRV bits in the SPI_CTL0 register according to the application s demand as describ...

Page 551: ...ister to the receive buffer after the last valid sample clock and RBNE receive buffer not empty will be set also The application should read SPI_DATA register to get the received data and this will clear the RBNE flag automatically In MRU and MRB modes hardware continuously sends clock signal to receive the next data frame while in full duplex master mode MFD hardware only receives the next data f...

Page 552: ...ion SPI works in quad write mode when QMOD is set and QRD is cleared in SPI_QCTL register In this mode MOSI MISO IO2 and IO3 are all used as output pins SPI begins to generate clock on SCK line and transmit data on MOSI MISO IO2 and IO3 as soon as data is written into SPI_DATA TBE is cleared and SPIEN is set Once SPI starts transmission it always checks TBE status at the end of a frame and stops w...

Page 553: ...o generate SCK clocks so the written data can be any value Once SPI starts transmission it always checks SPIEN and TBE status at the end of a frame and stops when condition is not met So software should always write dummy data into SPI_DATA to make SPI generate SCK The operation flow for receiving in quad mode 1 Configure clock prescaler clock polarity phase etc in SPI_CTL0 and SPI_CTL1 register b...

Page 554: ...for the last RBNE flag and then receive the last data Confirm that TBE 1 and TRANS 0 At last disable the SPI by clearing SPIEN bit MTU MTB STU STB Write the last data into SPI_DATA and wait until the TBE flag is set and then wait until the TRANS flag is cleared Disable the SPI by clearing SPIEN bit MRU MRB After getting the second last RBNE flag read out this data and delay for a SCK clock time an...

Page 555: ...is request and read data from the SPI_DATA register automatically 21 5 5 CRC function There are two CRC calculators in SPI one for transmission and the other for reception The CRC calculation uses the polynomial in SPI_CRCPOLY register Application can switch on the CRC function by setting CRCEN bit in SPI_CTL0 register The CRC calculators continuously calculate CRC for each bit transmitted and rec...

Page 556: ...re the SPI is disabled and the device is forced into slave mode The SPIEN and MSTMOD bit are write protection until the CONFERR is cleared The CONFERR bit of the slave cannot be set In a multi master configuration the device can be in slave mode with CONFERR bit set which means there might have been a multi master conflict for system control Rx Overrun Error RXORERR The RXORERR bit is set if a dat...

Page 557: ...egisters module including the TX buffer and RX buffer The clock generator is used to produce I2S communication clock in master mode The master control logic is implemented to generate the I2S_WS signal and control the communication in master mode The slave control logic is implemented to control the communication in slave mode according to the received I2SCK and I2S_WS The shift register handles t...

Page 558: ...that the data length is 24 bits or 32 bits two write or read operations to or from the SPI_DATA register are needed to complete a frame In the case that the data length is 16 bits only one write or read operation to or from the SPI_DATA register is needed to complete a frame When using 16 bit data packed in 32 bit frame 16 bit 0 is inserted by hardware automatically to extend the data to 32 bit fo...

Page 559: ... 16 bits and the second one should be the lower 16 bits Figure 21 15 I2S Phillips standard timing diagram DTLEN 01 CHLEN 1 CKPL 0 I2S_CK I2S_SD 24 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 8 bit 0 MSB Figure 21 16 I2S Phillips standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 24 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 8 bit 0 MSB When...

Page 560: ...extend the data to 32 bit format MSB justified standard For MSB justified standard I2S_WS and I2S_SD are updated on the falling edge of I2S_CK The SPI_DATA register is handled in the exactly same way as that for I2S Phillips standard The timing diagrams for each configuration are shown below Figure 21 19 MSB justified standard timing diagram DTLEN 00 CHLEN 0 CKPL 0 I2S_CK I2S_SD 16 bit data frame ...

Page 561: ..._CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB Figure 21 26 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB LSB justified standard For LSB justified standard I2S_WS and I2S_SD are updated on the falling edge of I2S_CK In the case that the cha...

Page 562: ...I_DATA register is a 16 bit data The high 8 bits of this 16 bit data are zeros and the lower 8 bits are D 23 16 The second data read from the SPI_DATA register is D 15 0 Figure 21 29 LSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit 0 frame 1 channel left frame 2 channel right I2S_WS 16 bit data MSB LSB Figure 21 30 LSB justified standard timing diagram DTLEN 00 CH...

Page 563: ...0 CHLEN 0 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB LSB frame 1 frame 2 Figure 21 33 PCM standard short frame synchronization mode timing diagram DTLEN 10 CHLEN 1 CKPL 0 I2S_CK I2S_SD 32 bit data MSB I2S_WS MSB LSB frame 1 frame 2 Figure 21 34 PCM standard short frame synchronization mode timing diagram DTLEN 10 CHLEN 1 CKPL 1 I2S_CK I2S_SD 32 bit data MSB I2S_WS MSB LSB frame 1 frame 2 Figu...

Page 564: ...1 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit 0 The timing diagrams for each configuration of the long frame synchronization mode are shown below Figure 21 39 PCM standard long frame synchronization mode timing diagram DTLEN 00 CHLEN 0 CKPL 0 I2S_CK I2S_SD 16 bits MSB I2S_WS MSB LSB frame 1 frame 2 13 bits Figure21 40 PCM standard long frame synchronization mode timing d...

Page 565: ...K I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits 8 bit 0 Figure 21 44 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits 8 bit 0 Figure 21 45 PCM standard long frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits ...

Page 566: ... I2SCLK DIV 2 OF 1 0 I2SCLK 8 DIV 2 OF 1 1 I2SCLK 4 DIV 2 OF The relationship between audio sampling frequency Fs and I2S bitrate is defined by the following formula Fs I2S bitrate number of bits per channel number of channels So in order to get the desired audio sampling frequency the clock generator needs to be configured according to the formulas listed in Table 21 6 Audio sampling frequency ca...

Page 567: ...ed by I2S and can be used by other functions I2S initialization sequence I2S initialization sequence contains five steps shown below In order to initialize I2S working in master mode all the five steps should be done In order to initialize I2S working in slave mode only step 2 step 3 step 4 and step 5 should be done Step 1 Configure the DIV 7 0 bits the OF bit and the MCKOEN bit in the SPI_I2SPSC ...

Page 568: ...g the left channel data should be written to the SPI_DATA register In order to switch off I2S it is mandatory to clear the I2SEN bit after the TBE flag is high and the TRANS flag is low I2S master reception sequence The RBNE flag is used to control the reception sequence As is mentioned before the RBNE flag indicates the receive buffer is not empty and an interrupt will be generated if the RBNEIE ...

Page 569: ...n to the SPI_DATA register before the master initiates the communication Software should write the next audio data into SPI_DATA register before the current data finishe Otherwise transmission underrun error occurs The TXURERR flag is set and an interrupt may be generated if the ERRIE bit in the SPI_CTL1 register is set In this case it is mandatory to switch off and switch on I2S to resume the com...

Page 570: ...ceive buffer and software can read the data by reading the SPI_DATA register I2S Transmitting On Going flag TRANS TRANS is a status flag to indicate whether the transfer is on going or not It is set and cleared by internal hardware and not controlled by software This flag doesn t generate any interrupt I2S channel side flag I2SCH This flag indicates the channel side information of the current tran...

Page 571: ...t Table 21 8 I2S interrupt Flag Name Description Clear Method Interrupt Enable bit TBE Transmit buffer empty Write SPI_DATA register TBEIE RBNE Receive buffer not empty Read SPI_DATA register RBNEIE TXURERR Transmission underrun error Read SPI_STAT register ERRIE RXORERR Reception overrun error Read SPI_DATA register and then read SPI_STAT register ...

Page 572: ...15 BDEN Bidirectional enable 0 2 line unidirectional transmit mode 1 1 line bidirectional transmit mode The information transfers between the MOSI pin in master and the MISO pin in slave 14 BDOEN Bidirectional Transmit Output Enable When BDEN is set this bit determines the direction of transfer 0 Work in receive only mode 1 Work in transmit only mode 13 CRCEN CRC Calculation Enable 0 CRC calculati...

Page 573: ...ect only when the SWNSSEN bit is set 7 LF LSB First Mode 0 Transmit MSB first 1 Transmit LSB first 6 SPIEN SPI Enable 0 SPI peripheral is disabled 1 SPI peripheral is enabled 5 3 PSC 2 0 Master Clock Prescaler Selection 000 PCLK 2 100 PCLK 32 001 PCLK 4 101 PCLK 64 010 PCLK 8 110 PCLK 128 011 PCLK 16 111 PCLK 256 PCLK means PCLK2 when using SPI0 or PCLK1 when using SPI1 and SPI2 2 MSTMOD Master Mo...

Page 574: ...NE bit is set 5 ERRIE Errors Interrupt Enable 0 Error interrupt is disabled 1 Error interrupt is enabled An interrupt is generated when the CRCERR bit or the CONFERR bit or the RXORERR bit or the TXURERR bit is set 4 3 Reserved Must be kept at reset value 2 NSSDRV Drive NSS Output 0 NSS output is disabled 1 NSS output is enabled If the NSS pin is configured as output the NSS pin is pulled low in m...

Page 575: ...curs This bit is set by hardware and cleared by a read operation on the SPI_DATA register followed by a read access to the SPI_STAT register 5 CONFERR SPI Configuration error Bit 0 No configuration fault occurs 1 Configuration fault occurred In master mode the NSS pin is pulled low in NSS hardware mode or SWNSS bit is low in NSS software mode This bit is set by hardware and cleared by a read or wr...

Page 576: ...ister SPI_DATA Address offset 0x0C Reset value 0x0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 DATA 15 0 Data transfer register The hardware has two buffers including transmit buffer and receive buffer Write data...

Page 577: ...ister has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCR 15 0 r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 RCR 15 0 RX CRC register When the CRCEN bit of SPI_CTL0 is set the hardware computes the CRC value of the received bytes and saves them in RCR register If the Data frame format is s...

Page 578: ...tion is based on CRC8 standard and saves the value in TCR 7 0 when the Data frame format is set to 16 bit data CRC calculation is based on CRC16 standard and saves the value in TCR 15 0 The hardware computes the CRC value after each transmitted bit when the TRANS is set a read to this register could return an intermediate value The different frame format LF bit of the SPI_CTL0 will get different C...

Page 579: ... synchronization mode 0 Short frame synchronization 1 long frame synchronization This bit has a meaning only when PCM standard is used This bit should be configured when I2S mode is disabled This bit is not used in SPI mode 6 Reserved Must be kept at reset value 5 4 I2SSTD 1 0 I2S standard selection 00 I2S Phillips standard 01 MSB justified standard 10 LSB justified standard 11 PCM standard These ...

Page 580: ... 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MCKOEN OF DIV 7 0 rw rw rw Bits Fields Descriptions 31 10 Reserved Must be kept at reset value 9 MCKOEN I2S_MCK output enable 0 I2S_MCK output is disabled 1 I2S_MCK output is enabled This bit should be configured when I2S mode is disabled This bit is not used in SPI mode 8 OF Odd factor for the prescaler 0 Real divider value is DIV 2 1...

Page 581: ...IO23_DRV Drive IO2 and IO3 enable 0 IO2 and IO3 are not driven in single wire mode 1 IO2 and IO3 are driven to high in single wire mode This bit is only available in SPI0 1 QRD Quad SPI mode read select 0 SPI is in quad wire write mode 1 SPI is in quad wire read mode This bit should be only be configured when SPI is not busy TRANS bit cleared This bit is only available in SPI0 0 QMOD Quad SPI mode...

Page 582: ... supported 22 3 Block diagram The DCI contains these modules Signal Processing Pixel FIFO FIFO controller window timing embedded sync detection DMA interface and control register Figure 22 1 DCI module block diagram HS VS Control Register Pixel FIFO FIFO Controler Window Timing Embedded Sync Detection Signal Processing PIX_DATA 13 0 AHB Interface DMA Request DMA Interface DCI_PixClk DCI_PixData 13...

Page 583: ...request every time the FIFO is not empty Control register provides register interface between DCI and software 22 4 Signal description Table 22 1 PINs used by DCI Direction Name Width Description Input DCI_PixClk 1 DCI Pixel Clock Input DCI_PixData 14 DCI Pixel Data Input DCI_Hs 1 DCI Horizontal Synchronization Input DCI_Vs 1 DCI Vertical Synchronization 22 5 Function overview 22 5 1 DCI hardware ...

Page 584: ...ed synchronization mode the 0xFF and 0x00 should not appear in pixel data to avoid mistake In embedded synchronization mode DCI starts to detect the sync codes after enabled and recover line frame synchronization information For example DCI starts to capture a new frame if it detects a Frame End code and then a Frame Start Code When detecting sync code it is possible to make DCI compare only a few...

Page 585: ...be triggered and DCI stops the capture 22 5 5 Pixel formats data padding and DMA DCI supports various pixel digital encoding formats including YCbCr422 RGB565 However DCI only receives these pixel data pads these pixels into a word and push into a pixel FIFO DCI doesn t perform any pixel format conversion or data processing and doesn t care about the detail of pixel format DCI uses a 32 bits width...

Page 586: ...iew in half word padding mode 2 b00 D1 13 0 2 b00 D0 13 0 2 b00 D3 13 0 2 b00 D2 13 0 2 b00 D5 13 0 2 b00 D4 13 0 2 b00 D7 13 0 2 b00 D6 13 0 22 6 Interrupts There are several status and error flags in DCI and interrupts may be asserted from these flags These status and error flags will assert global DCI interrupt if enabled by corresponding bit in DCI_INTEN These flags are cleared by writing into...

Page 587: ...e 14 DCIEN DCI Enable 0 DCI is disabled 1 DCI is enabled 13 12 Reserved Must keep the reset value 11 10 DCIF 1 0 Digital Camera Interface Format 00 8 bit data on every pixel clock 01 10 bit data on every pixel clock 10 12 bit data on every pixel clock 11 14 bit data on every pixel clock 9 8 FR 1 0 Frame Rate FR defines the frame capture rate in continuous capture mode 00 Capture All frames 01 Capt...

Page 588: ...nuous capture mode 1 Snapshot capture mode 0 CAP Capture Enable 0 Frame not captured 1 Frame is captured 22 7 2 Status register0 DCI_STAT0 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FV VS HS r r r Bits Fields Descriptions 31 3 Reserved Must keep t...

Page 589: ...lds Descriptions 31 5 Reserved Must keep the reset value 4 ELF End of Line Flag 0 No end of line flag 1 A line is captured by DCI 3 VSF Vsync Flag 0 No vsync flag 1 A vsync blanking detected 2 ESEF Embedded Synchronous Error Flag 0 No Embedded Synchronous Error Flag 1 A Embedded Synchronous Error detected 1 OVRF FIFO Overrun Flag 0 No FIFO Overrun 1 A FIFO overrun occurs 0 EFF End of Frame Flag 0 ...

Page 590: ...mbedded Synchronous Error Interrupt Enable 0 Embedded Synchronous Error Flag won t generate interrupt 1 Embedded Synchronous Error Flag will generate interrupt 1 OVRIE FIFO Overrun Interrupt Enable 0 FIFO Overrun won t generate interrupt 1 FIFO Overrun will generate interrupt 0 EFIE End of Frame Interrupt Enable 0 End of frame flag won t generate interrupt 1 End of frame flag will generate interru...

Page 591: ...7 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ELFC VSFC ESEFC OVRFC EFFC w w w w w Bits Fields Descriptions 31 5 Reserved Must keep the reset value 4 ELFC End of Line Flag Clear Write 1 to clear end of line flag 3 VSFC Vsync flag clear Write 1 to clear vsync flag 2 ESEFC Clear embedded synchronous Error Flag Write 1 to clear Embedded Synchronous Error F...

Page 592: ...ister DCI_SCUMSK Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FEM 7 0 LEM 7 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSM 7 0 FSM 7 0 rw rw Bits Fields Descriptions 31 24 FEM 7 0 Frame End Code unMask Bits in Embedded Synchronous Mode 23 16 LEM 7 0 Line End Code unMask Bits in Embedded Synchronous Mo...

Page 593: ...rst pixel in a line 22 7 10 Cropping window size register DCI_CWSZ Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved WVSZ 13 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WHSZ 13 0 rw Bits Fields Descriptions 31 30 Reserved Must keep the reset value 29 16 WVSZ 13 0 Window Vertical Size WVSZ X m...

Page 594: ...rd 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DT3 7 0 DT2 7 0 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DT1 7 0 DT0 7 0 r r Bits Fields Descriptions 31 24 DT3 7 0 Pixel Data 3 23 16 DT2 7 0 Pixel Data 2 15 8 DT1 7 0 Pixel Data 1 7 0 DT0 7 0 Pixel Data 0 ...

Page 595: ... 800 x 600 resolution Timing parameters is fully programmable Built in DMA engine to handle frame data copy 2 separate frame layers with window and blending function Support various pixel formats ARGB8888 RGB888 RGB565 etc Support CLUT Color Look Up Table and Color Keying format Dithering operation to low bits of a pixel 23 3 Block diagram Figure below shows the block diagram of the TLI module The...

Page 596: ...rizontal Synchronous Output VS 1 Vertical Synchronous Output DE 1 Data Enable Output PIXCLK 1 Pixel Clock Output RED 7 0 8 Pixel Red Data Output GREEN 7 0 8 Pixel Green Data Output BLUE 7 0 8 Pixel Blue Data 23 5 Function overview 23 5 1 LCD display timing LCD interface is a synchronous data interface with pixel clock pixel data and horizontal and vertical synchronous signals The figure below show...

Page 597: ...nly one AHB access interface so it will perform round robin arbitration between the 2 layers during pixels fetching if both layers are enabled FBADD in TLI_LxFBADDR register define the frame buffer address or fetching address of each layer FLL in TLI_LxFLLEN defines the line length in bytes of a frame If the length of a frame line in bytes is N program FLL with N 3 There may be some spacing betwee...

Page 598: ...es this entry as the RGB value Because the address of look up table is 8 bit PPU also fill LSBs with MSBs if L channel has bits less than 8 The entries in the look up tables are uninitialized after reset so the application should initialize the look up table with proper value using TLI_LxLUT register before display a look up table format layer The TLI_LxLUT is a write only register and a write ope...

Page 599: ...actor of current pixel is either normalization Pixel Alpha x normalization Specified Alpha or normalization Specified Alpha which is decided by register configuration 23 5 5 Layer configuration reload As is described above each layer has its own frame buffer pixel format window default color configuration registers and each register has a shadow register A shadow register shares the same address w...

Page 600: ...e is used to display a 24 bit data Application may switch on this function using DFEN bit in TLI_CTL register 23 5 7 Interrupt There are several status and error flags in TLI and interrupt may be asserted from these flags The status flags will assert global interrupt while the error flags will assert error interrupt Table 23 3 Status flags Status Flag Name Description LMF Line Mark Flag LCRF Layer...

Page 601: ...alue 27 16 HPSZ 11 0 Size of the horizontal synchronous pulse The HPSZ value should be configured to the pixels number of horizontal synchronous pulse minus 1 15 12 Reserved Must keep the reset value 11 0 VPSZ 11 0 Size of the vertical synchronous pulse The VPSZ value should be configured to the pixels number of vertical synchronous pulse minus 1 23 6 2 Back porch size register TLI_BPSZ Address of...

Page 602: ...2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved HASZ 11 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VASZ 11 0 rw Bits Fields Descriptions 31 28 Reserved Must keep the reset value 27 16 HASZ 11 0 Size of the horizontal active area width plus back porch and synchronous pulse The HASZ value should be configured to the pixels number of horizontal active area width plus back porc...

Page 603: ...ous pulse and front porch The VTSZ value should be configured to the pixels number of vertical active area height plus back porch front porch and synchronous pulse minus 1 23 6 5 Control register TLI_CTL Address offset 0x18 Reset value 0x0000 2220 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HPPS VPPS DEPS CLKPS Reserved DFEN rw rw rw rw rw 15 14 ...

Page 604: ...Fixed to 2 read only 11 Reserved Must keep the reset value 10 8 GDB 2 0 Green channel Dither Bits Number Fixed to 2 read only 7 Reserved Must keep the reset value 6 4 BDB 2 0 Blue channel Dither Bits Number Fixed to 2 read only 3 1 Reserved Must keep the reset value 0 TLIEN TLI enable bit 0 TLI disable 1 TLI enable 23 6 6 Reload layer register TLI_RL Address offset 0x24 Reset value 0x0000 0000 Thi...

Page 605: ...LI_BGC Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BVR 7 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BVG 7 0 BVB 7 0 rw rw Bits Fields Descriptions 31 24 Reserved Must keep the reset value 23 16 BVR 7 0 Background Value Red 15 8 BVG 7 0 Background Value Green 7 0 BVB 7 0 Background Value Blue 23...

Page 606: ...n interrupt 0 LMIE Line Mark Interrupt Enable 0 Line mark flag won t generate an interrupt 1 Line mark flag will generate an interrupt 23 6 9 Interrupt flag register TLI_INTF Address offset 0x38 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LCRF TEF FEF LMF r r r r Bits...

Page 607: ...0 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LCRC TEC FEC LMC w w w w Bits Fields Descriptions 31 4 Reserved Must keep the reset value 3 LCRC Layer Configuration Reloaded Flag Clear Write 1 to clear layer configuration reloaded flag 2 TEC Transaction Error Flag Clear Write 1 to clear transaction error flag 1 FEC FIFO Error Flag Clear Write 1 to clear FIFO error flag 0 LMC ...

Page 608: ... to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HPOS 15 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPOS 15 0 r Bits Fields Descriptions 31 16 HPOS 15 0 Horizontal Position Horizontal position of the current displayed pixel 15 0 VPOS 15 0 Vertical Position Vertical position of the current displayed pixel 23 6 13 Status register TLI_STAT Address offset 0x48 Reset value ...

Page 609: ... register and HASZ in TLI_ASZ register 0 VDE Current VDE status 0 VPOS in TLI_CPPOS register is not between the VBPSZ in TLI_BPSZ register and VASZ in TLI_ASZ register 1 VPOS in TLI_CPPOS register is between the VBPSZ in TLI_BPSZ register and VASZ in TLI_ASZ register 23 6 14 Layer x control register TLI_LxCTL Address offset 0x84 0x80 x x 0 or 1 Reset value 0x0000 0000 This register has to be acces...

Page 610: ...88 0x80 x x 0 or 1 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved WRP 11 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WLP 11 0 rw Bits Fields Descriptions 31 28 Reserved Must keep the reset value 27 16 WRP 11 0 Window Right Position 15 12 Reserved Must keep the reset value 11 0 WLP 11 0 Window Left Position 23...

Page 611: ... by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved CKEYR 7 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CKEYG 7 0 CKEYB 7 0 rw rw Bits Fields Descriptions 31 24 Reserved Must keep the reset value 23 16 CKEYR 7 0 Color Key Red 15 8 CKEYG 7 0 Color Key Green 7 0 CKEYB 7 0 Color Key Blue If the pixel RGB value in a layer equals the value in TLI_LxCKEY the pixel RGB value is reset ...

Page 612: ...ARGB1555 100 ARGB4444 101 L8 110 AL44 111 AL88 23 6 19 Layer x specified alpha register TLI_LxSA Address offset 0x98 0x80 x x 0 or 1 Reset value 0x0000 00FF This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SA 7 0 rw Bits Fields Descriptions 31 8 Reserved Must keep the reset value 7 0 SA 7 0 Speci...

Page 613: ...yer is disabled or outside the window defined in TLI_LxHPOS and TLI_LxVPOS 23 6 21 Layer x blending register TLI_LxBLEND Address offset 0xA0 0x80 x x 0 or 1 Reset value 0x0000 0607 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ACF1 2 0 Reserved ACF2 2 0 rw rw Bits Fields Descriptions 31 11 Res...

Page 614: ...80 x x 0 or 1 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FBADD 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FBADD 15 0 rw Bits Fields Descriptions 31 0 FBADD 31 0 Frame Buffer base Address The base address of frame buffer 23 6 23 Layer x frame line length register TLI_LxFLLEN Address offset 0xB0 0x80 x x 0 or 1 Reset va...

Page 615: ...eset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FTLN 10 0 rw Bits Fields Descriptions 31 11 Reserved Must keep the reset value 10 0 FTLN 10 0 Frame Total Line Number This value defines the line number in a frame 23 6 25 Layer x look up table register TLI_LxLUT Address offs...

Page 616: ...Look Up Table Write Address The entry at this address in LUT will be updated with the value of RED GREEN and BLUE written 23 16 TR 7 0 Red Channel of a LUT entry 15 8 TG 7 0 Green Channel of a LUT entry 7 0 TB 7 0 Blue Channel of a LUT entry ...

Page 617: ...ng MMC Full support for Multimedia Card System Specification Version 4 2 and previous versions Card and three different data bus modes 1 bit default 4 bit and 8 bit SD Card Full support for SD Memory Card Specifications Version 2 0 SD I O Full support for SD I O Card Specification Version 2 0 card and two different data bus modes 1 bit default and 4 bit CE ATA Full compliance with CE ATA digital p...

Page 618: ...se commands send a data block successfully by CRC bits Both read and write operations allow either single or multiple block transmission A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read The basic transaction on the bus is the command response transaction refer to Figure 24 1 SDIO no response and no data operations This type of...

Page 619: ...eration Host to Device Host to Device Data transfers to from SD memory cards SD I O cards both IO only card and combo card and CE ATA device are done in data blocks Data transfers to from MMC are done in data blocks or streams Figure 24 4 SDIO sequential read operation and Figure 24 5 SDIO sequential write operation are the stream read and write operation Figure 24 4 SDIO sequential read operation...

Page 620: ...a unit and generates signals to cards The signals are descript bellow SDIO_CLK The SDIO_CLK is the clock provided to the card Each cycle of this signal directs a one bit transfer on the command line SDIO_CMD and on all the data lines SDIO_DAT The SDIO_CLK frequency can vary between 0 MHz and 20 MHz for a Multimedia Card V3 31 between 0 and 48 MHz for a Multimedia Card V4 2 or between 0 and 25 MHz ...

Page 621: ...configured by setting CLKPWRSAV bit in SDIO_CLKCTL register which implements close the SDIO_CLK when the bus is idle The clock management generates SDIO_CLK to card The SDIO_CLK is generated by a divider of SDIOCLK when CLKBYP bit in SDIO_CLKCTL register is 0 or directly SDIOCLK when CLKBYP bit in SDIO_CLKCTL register is 1 The Hardware clock control is enabled by setting HWCLKEN in SDIO_CLKCTL reg...

Page 622: ...ata transfer 1 The data transfer complete CS_Send 2 CSM disabled CS_Idle CS_Send Sending the command 1 The command transmitted has response CS_Wait 2 The command transmitted doesn t have response CS_Idle 3 CSM disabled CS_Idle CS_Wait Wait for the start bit of the response 1 Receive the response detected the start bit CS_Receive 2 Timeout is reached without receiving the response CS_Idle 3 CSM dis...

Page 623: ...data from card when DATADIR in SDIO_DATACTL register is 1 The data unit also generates the data status flags defined in SDIO_STAT register Data state machine DS_Idle The data unit is inactive waiting for send and receive 1 DSM enabled and data transfer direction is from host to card DS_WaitS 2 DSM enabled and data transfer direction is from card to host DS_WaitR 3 DSM enabled and Read Wait Started...

Page 624: ...registers data FIFO and generates interrupt and DMA request It includes a data FIFO unit registers unit and the interrupt DMA logic The interrupt logic generates interrupt when at least one of the selected status flags is high An interrupt enable register is provided to allow the logic to generate a corresponding interrupt The DMA interface provides a method for fast data transfers between the SDI...

Page 625: ... FIFO The data FIFO unit has a data buffer used as transmit and receive FIFO The FIFO contains a 32 bit wide 32 word deep data buffer The transmit FIFO is used when write data to card and TXRUN in SDIO_STAT register is 1 The data to be transferred is written to transmit FIFO by AHB bus the data unit in SDIO adapter read data from transmit FIFO and then send the data to card The receive FIFO is use...

Page 626: ...configuration the card is working in These modes can be changed by the host by means of the SWITCH command The host can use CMD8 just MMC supports this command to get the content of this register RCA register The writable 16 bit relative card address register carries the card address that is published by the card during the card identification This address is used for the addressed host card commu...

Page 627: ...ys starts with a start bit always 0 followed by the bit indicating the direction of transmission host 1 The next 6 bits indicate the index of the command this value being interpreted as a binary coded number between 0 and 63 Some commands need an argument e g an address which is coded by 32 bits A value denoted by x in the table above indicates this variable is dependent on the command All command...

Page 628: ...on Other interface configuration settings such as bus width may require additional MMC commands also be supported See the MMC reference CE ATA makes use of the following MMC commands CMD0 GO_IDLE_STATE CMD12 STOP_TRANSMISSION CMD39 FAST_IO CMD60 RW_MULTIPLE_REGISTER CMD61 RW_MULTIPLE_BLOCK GO_IDLE_STATE CMD0 STOP_TRANSMISSION CMD12 and FAST_IO CMD39 are as defined in the MMC reference RW_MULTIPLE_...

Page 629: ...ck write erase write protection Lock card application specific I O mode switch reserved CMD17 M CMD18 M CMD19 M CMD20 M CMD23 M CMD24 M CMD25 M CMD26 M CMD27 M CMD28 M CMD29 M CMD30 M CMD32 M CMD33 M CMD34 O CMD35 O CMD36 O CMD37 O CMD38 M CMD39 CMD40 CMD42 CMD50 O CMD52 O CMD53 O CMD55 M CMD56 M CMD57 O CMD60 M CMD61 M ACMD6 M ACMD13 M ACMD22 M ACMD23 M ...

Page 630: ... describe in detail all bus commands The responses R1 R7 are defined in Responses The registers CID CSD and DSR are described in Card registers The card shall ignore stuff bits and reserved bits in an argument Table 24 4 Basic commands class 0 Cmd index type argument Response format Abbreviation Description CMD0 bc 31 0 stuff bits GO_IDLE_STATE Resets all cards to idle state CMD1 bc 31 0 OCR witho...

Page 631: ... and gets deselected by any other address address 0 deselects the card CMD8 bcr 31 12 reserved bits 11 8 supply voltage VHS 7 0 check pattern R7 SEND_IF_COND Sends SD Memory Card interface condition which includes host supply voltage information and asks the card whether card supports voltage Reserved bits shall be set to 0 CMD8 adtc 31 0 stuff bits R1 SEND_EXT_CSD For MMC only The card sends its ...

Page 632: ...n bytes for all following block commands read write lock Default is 512 Bytes Set length is valid for memory access commands only if partial block read operation are allowed in CSD In the case of a High Capacity SD Memory Card block length set by CMD16 command does not affect the memory read and write commands Always 512 Bytes fixed block length is used In both cases if block length is set larger ...

Page 633: ...ddress until a STOP_TRANSMISSION follows CMD20 adtc 31 0 data address R1 WRITE_DAT_UNT IL_STOP Writes data stream from the host starting at the given address until a STOP_TRANSMISSION follows Note The transferred data must not cross a physical block boundary unless READ_BLK_MISALIGN is set in the CSD register Table 24 7 Block Oriented write commands class 4 Cmd index type argument Response format ...

Page 634: ...rst programming Normally this command is reserved for the manufacturer CMD27 adtc 31 0 stuff bits R1 PROGRAM_CSD Programming of the programmable bits of the CSD Note 1 The data transferred shall not cross a physical block boundary unless WRITE_BLK_MISALIGN is set in the CSD In the case that write partial blocks is not supported then the block length default block length given in CSD 2 Data address...

Page 635: ...nds class 6 Cmd index type argument Response format Abbreviation Description CMD28 ac 31 0 data address R1b SET_WRITE_PROT If the card has write protection features this command sets the write protection bit of the addressed group The properties of write protection are coded in the card specific data WP_GRP_SIZE A High Capacity SD Memory Card does not support this command CMD29 ac 31 0 data addres...

Page 636: ... capacity support information HCS and asks the accessed card to send its operating condition register OCR content in the response HCS is effective when card receives SEND_IF_COND command CCS bit is assigned to OCR 30 ACMD42 ac 31 1 stuff bits 0 set_cd R1 SET_CLR_CAR D_DETECT Connect 1 Disconnect 0 the 50K pull up resistor on CD DAT3 pin 1 of the card ACMD51 adtc 31 0 stuff bits R1 SEND_SCR Reads t...

Page 637: ...CA 15 register write flag 14 8 register address 7 0 register data R4 FAST_IO Used to write and read 8 bit register data fields The command addresses a card and a register and provides the data for writing if the write flag is set The R4 response contains data read from the addressed register if the write flag is cleared to 0 This command accesses application dependent registers which are not defin...

Page 638: ...ng of a large number of I O registers with a single command Note 1 CMD39 CMD40 are only for MMC 2 CMD52 CMD53 are only for SD I O card Table 24 13 Switch function commands class 10 Cmd index type argument Response format Abbreviation Description CMD6 adtc 31 Mode 0 Check function 1 Switch function 30 24 reserved 23 20 reserved for function group 6 0h or Fh 19 16 reserved for function group 5 0h or...

Page 639: ...orts additional response types named R4 and R5 but they are not exactly the same for SD I O Card and MMC Responses format Responses have two formats as show in Figure 24 8 Response Token Format all responses are sent on the CMD line The code length depends on the response type Except R2 is 136 bits length others are all 48 bits length Figure 24 8 Response Token Format 0 1 Content CRC 1 Total lengt...

Page 640: ...y after receiving these commands based on its state prior to the command reception The Host shall check for busy at the response R2 CID CSD register Code length is 136 bits The contents of the CID register are sent as a response to the commands CMD2 and CMD10 The contents of the CSD register are sent as a response to CMD9 Only the bits 127 1 of the CID and CSD are transferred the reserved bit 0 of...

Page 641: ...The SDIO card receive the CMD5 will respond with a unique SD I O response R4 Table 24 18 Response R4 for SD I O Bit position 47 46 45 40 39 38 36 35 34 32 31 30 8 7 1 0 Width 1 1 6 1 3 1 3 1 23 7 1 Value 0 0 11111 1 x x x 000 x x 11111 11 1 descripti on start bit transmissi on bit Reserv ed C Number of I O functions Memory Present Stuff Bits S18A I O OCR Reserv ed end bit R5 Interrupt request For ...

Page 642: ...escription start bit transmission bit CMD3 New published RCA of the card card status bits 23 22 19 12 0 CRC7 end bit R7 Card interface condition For SD memory only Code length is 48 bits The card support voltage information is sent by the response of CMD8 Bits 19 16 indicate the voltage range that the card supports The card that accepted the supplied voltage returns R7 response In the response the...

Page 643: ... b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 DAT0 4 bit data packet format Figure 24 10 4 bit data bus width Start bit End bit 1st Byte 2nd Byte 3rd Byte nth Byte 0 CRC 1 DAT3 0 CRC 1 DAT2 0 CRC 1 DAT1 0 CRC 1 DAT0 b7 b3 b6 b2 b5 b1 b4 b0 b7 b3 b6 b2 b5 b1 b4 b0 b7 b3 b6 b2 b5 b1 b4 b0 b7 b3 b6 b2 b5 b1 b4 b0 8 bit data packet format Figure 24 11 8 bit data bus width Start bit End bit 1st Byte...

Page 644: ...oon as the response reporting the error is sent out S Status bit These bits serve as information fields only and do not alter the execution of the command being responded to These bits are persistent they are set and cleared in accordance with the card status R Exceptions are detected by the card during the command interpretation and validation phase Response Mode X Exceptions are detected by the ...

Page 645: ...error 1 error Set when a sequence or password error has been detected in lock unlock card command C 23 COM_CRC_ERROR ER 0 no error 1 error The CRC check of the previous command failed B 22 ILLEGAL_COMMAND ER 0 no error 1 error Command not legal for the card state B 21 CARD_ECC_FAILED ERX 0 success 1 failure Card internal ECC was applied but failed to correct the data C 20 CC_ERROR ERX 0 no error 1...

Page 646: ...cause an out of erase sequence command was received C 12 9 CURRENT_STATE SX 0 idle 1 ready 2 identification 3 stand by 4 transfer 5 send data 6 receive data 7 programming 8 disconnect 9 14 reserved 15 reserved for I O mode The state of the card when receiving the command If the command execution causes a state change it will be visible to the host in the response to the next command The four bits ...

Page 647: ...3 can be sent to a card only in transfer state card is selected The SD Status structure is described below The same abbreviation for type and clear condition were used as for the Card Status above Table 24 24 SD status Bits Identifier Type Value Description Clear Condition 511 5 10 DAT_BUS_WIDTH SR 00 1 default 01 reserved 10 4 bit width 11 reserved Shows the currently defined data bus width that ...

Page 648: ...e below A 401 4 00 ERASE_OFFSET SR Fixed offset value added to erase time See below A 399 3 12 reserved 311 0 reserved for manufacturer SIZE_OF_PROTECTED_AREA Setting this field differs between SDSC and SDHC SDXC In case of SDSC Card the capacity of protected area is calculated as follows Protected Area SIZE_OF_PROTECTED_AREA_ MULT BLOCK_LEN SIZE_OF_PROTECTED_AREA is specified by the unit in MULT ...

Page 649: ...e field PERFORMANCE_MOVE Value Definition 00h Sequential Write 01h 1 MB sec 02h 2 MB sec FEh 254 MB sec FFh Infinity AU_SIZE This 4 bit field indicates AU Size and the value can be selected from 16 KB Table 24 26 AU_SIZE field AU_SIZE Value Definition 0h Not Defined 1h 16 KB 2h 32 KB 3h 64 KB 4h 128 KB 5h 256 KB 6h 512 KB 7h 1 MB 8h 2 MB 9h 4 MB Ah 8 MB Bh 12 MB Ch 16 MB Dh 24 MB Eh 32 MB Fh 64 MB...

Page 650: ...finition 0000h Erase Time out Calculation is not supported 0001h 1 AU 0002h 2 AU 0003h 3 AU FFFFh 65535 AU ERASE_TIMEOUT This 6 bit field indicates the TERASE and the value indicates erase timeout from offset when multiple AUs are erased as specified by ERASE_SIZE The range of ERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can choose any combination of ERASE_SIZE and ER...

Page 651: ...he reset command CMD0 is only used for memory or the memory portion of Combo cards In order to reset an I O only card or the I O portion of a combo card use CMD52 to write 1 to the RES bit in the CCCR Cards in Inactive State are not affected by this command After power on by the host all cards are in Idle State including the cards that have been in Inactive State before After power on or CMD0 all ...

Page 652: ...Y and SDIO COMBO cards The identification process sequence includes the following steps Check if the card is connected Identify the card type SD MMC CE ATA or SD I O Send CMD5 first If a response is received then the card is SD I O If not send ACMD41 if a response is received then the card is SD Otherwise the card is an MMC or CE ATA Initialization the card according to the card type Use a clock s...

Page 653: ...r WRITE_BLK_MISALIGN is not set the card will detect the block misalignment error before the beginning of the first misaligned block The card shall set the ADDRESS_ERROR error bit in the status register and ignore all further data transfer at the same time The write operation will also be aborted if the host tries to write data on a write protected area In this case however the card will set the W...

Page 654: ...RECV flag is set 5 Write data to SDIO_FIFO 6 Software should look for data error interrupts If required software can terminate the data transfer by sending the STOP command CMD12 7 When a DTEND interrupt is received the data transfer is over For an open ended block transfer if the byte count is 0 the software must send the STOP command If the byte count is not 0 then upon completion of a transfer ...

Page 655: ...le block and multiple block transfers For CE ATA first using CMD60 to write the ATA task file then using CMD61 to read the data After writing to the CMD register the host starts executing the command when the command is sent to the bus the CMDRECV flag is set 5 Software should look for data error interrupts If required software can terminate the data transfer by sending a STOP command 6 The softwa...

Page 656: ...er state Stream read There is a stream oriented data transfer controlled by READ_DAT_UNTIL_STOP CMD11 This command instructs the card to send its data starting at a specified address until the host sends a STOP_TRANSMISSION command CMD12 The stop command has an execution delay due to the serial command transmission The data transfer stops after the end bit of the stop command If the host provides ...

Page 657: ...T CMD35 ERASE_WR_BLK_START CMD32 command next it defines the last address of the range using the ERASE_GROUP_END CMD36 ERASE_WR_BLK_END CMD33 command and finally it starts the erase process by issuing the ERASE CMD38 command The address field in the erase commands is an Erase Group address in byte units The card will ignore all LSB s below the Erase Group size effectively rounding the address down...

Page 658: ...to protect data against erase or write three methods for the cards are supported in the card CSD register for card protection optional The entire card may be write protected by setting the permanent or temporary write protect bits in the CSD Some cards support write protection of groups of sectors by setting the WP_GRP_ENABLE bit in the CSD It is defined in units of WP_GRP_SIZE erase groups as spe...

Page 659: ...rred data block includes all the required information of the command password setting mode PWD itself card lock unlock etc Table 24 31 Lock card data structure describes the structure of the command data block Table 24 31 Lock card data structure Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Reserved all set to 0 ERASE LOCK_UNLOCK CLR_PWD SET_PWD 1 PWDS_LEN 2 Password data PWD PWDS_LEN 1 ...

Page 660: ...ew password and its size will be saved in the PWD and PWD_LEN registers respectively Reset the password Select a card CMD7 if not previously selected Define the block length CMD16 given by the 8 bit card lock unlock mode the 8 bit password size in bytes and the number of bytes of the currently used password Send the card lock unlock command with the appropriate data block size on the data line inc...

Page 661: ...for read suspend that does not need specific hardware implementation SD I O read wait operation The optional Read Wait RW operation is defined only for the SD 1 bit and 4 bit modes The Read Wait operation allows a host to signal a card that is executing a read multiple CMD53 operation to temporarily stall the data transfer while allowing the host to send commands to any function within the SD I O ...

Page 662: ... interval while receiving a block even if Read Wait start is set the Read Wait interval will start after the CRC is received The RWSTOP bit has to be cleared to start a new Read Wait operation During the Read Wait interval the SDIO can detect SD I O interrupts on SDIO_DAT 1 SD I O suspend resume operation Within a multi function SD I O or a Combo card there are multiple devices I O and memory that...

Page 663: ... before stopping the data transaction The application should continue reading receive FIFO until the FIFO is empty and the DSM goes Idle state automatically Interrupts In order to allow the SD I O card to interrupt the host an interrupt function is added to a pin on the SD interface Pin number 8 which is used as SDIO_DAT 1 when operating in the 4 bit SD mode is used to signal the card s interrupt ...

Page 664: ...multi block read and Figure 24 18 Multiple block 4 Bit write interrupt cycle timing shows the operation for an interrupt during a 4 bit multi block write Figure 24 17 Multiple block 4 Bit read interrupt cycle timing SDIO_CLK DAT0 Command read data CMD DAT1 DAT1 mode S E Response S E Data S E interrupt data data int Data S E Data S E Data S E int 2 CLK 2 CLK data Figure 24 18 Multiple block 4 Bit w...

Page 665: ...the device it should issue a FAST_IO CMD39 command to read the ATA Status register to determine the ending status for the ATA command Command completion disable signal The host may cancel the ability for the device to return a command completion signal by issuing the command completion signal disable The host shall only issue the command completion signal disable when it has received an R1b respon...

Page 666: ...ut or output 00 SDIO power off SDIO cmd data state machine reset to IDLE clock to card stopped no cmd data output to card 01 Reserved 10 Reserved 11 SDIO Power on Note Between Two write accesses to this register it needs at least 3 SDIOCLK 2 PCLK2 which used to sync the registers to SDIOCLK clock domain 24 8 2 Clock control register SDIO_CLKCTL Address offset 0x04 Reset value 0x0000 0000 This regi...

Page 667: ... 00 1 bit SDIO card bus mode selected 01 4 bit SDIO card bus mode selected 10 8 bit SDIO card bus mode selected 10 CLKBYP Clock bypass enable bit This bit defines the SDIO_CLK is directly SDIOCLK or not 0 NO bypass the SDIO_CLK refers to DIV bits in SDIO_CLKCTL register 1 Clock bypass the SDIO_CLK is directly from SDIOCLK SDIOCLK 1 9 CLKPWRSAV SDIO_CLK clock dynamic switch on off for power saving ...

Page 668: ...ssage contains an argument this field must update before writing SDIO_CMDCTL register when sending a command 24 8 4 Command control register SDIO_CMDCTL Address offset 0x0C Reset value 0x0000 0000 The SDIO_CMDCTL register contains the command index and other command control bits to control command state machine This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 ...

Page 669: ...mand state machine enable 9 WAITDEND Waits for ends of data transfer If this bit is set the command state machine starts to send a command must wait the end of data transfer 0 no effect 1 Wait the end of data transfer 8 INTWAIT Interrupt wait instead of timeout This bit defines the command state machine to wait card interrupt at CS_Wait state in command state machine If this bit is set no command ...

Page 670: ... short response of R3 the content of this register is undefined 24 8 6 Response register SDIO_RESPx x 0 3 Address offset 0x14 4 x x 0 3 Reset value 0x0000 0000 These register contains the content of the last card response received This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESPx 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESPx 15 0 r Bits Fie...

Page 671: ...eout period These bits define the data timeout period count by SDIO_CLK When the DSM enter the state WaitR or BUSY the internal counter which loads from this register starts decrement The DSM timeout and enter the state Idle and set the DTTMOUT flag when the counter decreases to 0 Note The data timeout register and the data length register must be updated before being written to the data control r...

Page 672: ...ls the DSM This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IOEN RWTYPE RWSTOP RWEN BLKSZ 3 0 DMAEN TRANS MOD DATADIR DATAEN rw rw rw rw rw rw rw rw rw Note Between Two write accesses to this register it needs at least 3 SDIOCLK 2 PCLK2 which used to sync the registers to SDIOCLK clock domain 24 ...

Page 673: ...block size These bits defined the block size when data transfer is block transfer 0000 block size 20 1 byte 0001 block size 21 2 bytes 0010 block size 22 4 bytes 0011 block size 23 8 bytes 0100 block size 24 16 bytes 0101 block size 25 32 bytes 0110 block size 26 64 bytes 0111 block size 27 128 bytes 1000 block size 28 256 bytes 1001 block size 29 512 bytes 1010 block size 210 1024 bytes 1011 bloc...

Page 674: ...RFE TFE RFF TFF r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFH TFH RXRUN TXRUN CMDRUN DTBLK END STBITE DTEND CMD SEND CMD RECV RXORE TXURE DTTMOU T CMD TMOUT DTCRC ERR CCRCER R r r r r r r r r r r r r r r r r Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 ATAEND CE ATA command completion signal received only for CMD61 22 SDIOINT SD I O interrupt received 21 RXDTV...

Page 675: ...onse required 6 CMDRECV Command response received CRC check passed 5 RXORE Received FIFO overrun error occurs 4 TXURE Transmit FIFO underrun error occurs 3 DTTMOUT Data timeout The data timeout period depends on the SDIO_DATATO register 2 CMDTMOUT Command response timeout The command timeout period has a fixed value of 64 SDIO_CLK clock periods 1 DTCRCERR Data block sent received CRC check failed ...

Page 676: ... clear the flag 8 DTENDC DTEND flag clear bit Write 1 to this bit to clear the flag 7 CMDSENDC CMDSEND flag clear bit Write 1 to this bit to clear the flag 6 CMDRECVC CMDRECV flag clear bit Write 1 to this bit to clear the flag 5 RXOREC RXORE flag clear bit Write 1 to this bit to clear the flag 4 TXUREC TXURE flag clear bit Write 1 to this bit to clear the flag 3 DTTMOUTC DTTMOUT flag clear bit Wr...

Page 677: ...o enable the interrupt 21 RXDTVALIE Data valid in receive FIFO interrupt enable Write 1 to this bit to enable the interrupt 20 TXDTVALIE Data valid in transmit FIFO interrupt enable Write 1 to this bit to enable the interrupt 19 RFEIE Receive FIFO empty interrupt enable Write 1 to this bit to enable the interrupt 18 TFEIE Transmit FIFO empty interrupt enable Write 1 to this bit to enable the inter...

Page 678: ...bit to enable the interrupt 4 TXUREIE Transmit FIFO underrun error interrupt enable Write 1 to this bit to enable the interrupt 3 DTTMOUTIE Data timeout interrupt enable Write 1 to this bit to enable the interrupt 2 CMDTMOUTIE Command response timeout interrupt enable Write 1 to this bit to enable the interrupt 1 DTCRCERRIE Data CRC fail interrupt enable Write 1 to this bit to enable the interrupt...

Page 679: ...ite to or read from the FIFO 24 8 15 FIFO data register SDIO_FIFO Address offset 0x80 Reset value 0x0000 0000 This register occupies 32 entries of 32 bit words the address offset is from 0x80 to 0xFC This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIFODT 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFODT 15 0 rw Bits Fields Descriptions 31 0 FIFOD...

Page 680: ...ble parameter configuration as defined in the controlling register 25 2 Characteristics Supported external memory SRAM PSRAM SQPI PSRAM ROM NOR Flash 8 bit or 16 bit NAND Flash 16 bit PC Card Synchronous DRAM SDRAM Protocol translation between the AMBA and the multitude of external memory protocol Offering a variety of programmable timing parameters to meet user s specific needs Each bank has its ...

Page 681: ...HCLK from clock controller EXMC interrupt to NVIC NOR PSRAM Pins SDRAM Controller EXMC_SDCKE 1 0 EXMC_SDNE 1 0 EXMC_SDNRAS EXMC_SDNCAS EXMC_SDNWE EXMC_SDCLK PSRAM SDRAM Shared Pin SDRAM Pins Shared Pins NOR PSRAM NAND Shared Pin EXMC_NIOS16 25 3 2 Basic regulation of EXMC access EXMC is the conversion interface between AHB bus and external device protocol 32 bit of AHB read write accesses can be s...

Page 682: ...56M 0x6000 0000 0x6FFF FFFF 0x7000 0000 0x7FFF FFFF 0x8000 0000 0x9FFF FFFF 0x8FFF FFFF 0x9000 0000 Address Banks Supported memory type SDRAM Device0 256M SDRAM Device1 256M 0xC000 0000 0xCFFF FFFF 0xD000 0000 0xDFFF FFFF SDRAM NAND PC Card NOR PSRAM SQPI PSRAM EXMC access space is divided into multiple banks Each bank is 256 Mbytes The first bank Bank0 is further divided into four Regions and eac...

Page 683: ...nal memory may not be byte accessed this will lead to address inconsistency EXMC can adjust HADDR to accommodate the data width of the external memory according to the following rules When data bus width of the external memory is 8 bits In this case the memory address is byte aligned HADDR 25 0 is connected to EXMC_A 25 0 and then the EXMC_A 25 0 is connected to the external memory address lines W...

Page 684: ...ory Space Attribute Memory Space Common Memory Space Attribute Memory Space I O Memory Space Bank1 Bank2 Bank3 0x7000_0000 0x73FF_FFFF 0x7800_0000 0x7BFF_FFFF 0x8000_0000 0x83FF_FFFF 0x8800_0000 0x8BFF_FFFF 0x9000_0000 0x93FF_FFFF 0x9800_0000 0x9BFF_FFFF 0x9C00_0000 0x9FFF_FFFF Address Memory Space EXMC Memory Bank NAND address mapping For NAND Flash the common space and the attribute space are fu...

Page 685: ...atch enable ALE signal automatically in address transfer phase ALE is mapped to EXMC_A 17 Command area This area is where the NAND Flash access command should be issued by the software the EXMC will pull the command latch enable CLE signal automatically in command transfer phase CLE is mapped to EXMC_A 16 Data area This area is where the NAND Flash read write data should be accessed When the EXMC ...

Page 686: ... bank0 which is designed to support NOR Flash PSRAM SRAM ROM and honeycomb RAM external memory EXMC has 4 independent chip select signals for each of the 4 sub banks within bank0 named NE x x 0 1 2 3 Other signals for NOR PSRAM access are shared Each sub bank has its own set of configuration register but only sub bank 0 support SQPI PSRAM access and owns its corresponding unique register Note In a...

Page 687: ... Bus EXMC_NE x Output Async Sync Chip selection x 0 1 2 3 EXMC_NOE Output Async Sync Read enable EXMC_NWE Output Async Sync Write enable EXMC_NWAIT Input Async Sync Wait input signal EXMC_NL NADV Output Async Sync Latch enable address valid enable NADV EXMC_NBL 1 Output Async Sync Upper byte enable EXMC_NBL 0 Output Async Sync Lower byte enable Table 25 4 SQPI PSRAM signal description EXMC Pin Dir...

Page 688: ...Async W 8 16 Use of byte lanes EXMC_NBL 1 0 Async R 16 16 Async W 16 16 Async R 32 16 Split into 2 EXMC accesses Async W 32 16 Split into 2 EXMC accesses Sync R 16 16 Sync R 32 16 Sync W 8 16 Use of byte lanes EXMC_NBL 1 0 Sync W 16 16 Sync W 32 16 Split into 2 EXMC accesses SRAM and ROM Async R 8 8 Async R 8 16 Async R 16 8 Split into 2 EXMC accesses Async R 16 16 Async R 32 8 Split into 4 EXMC a...

Page 689: ...K 2 256 AHLD Address hold time Async muxed HCLK 1 16 ASET Address setup time Async HCLK 1 16 Table 25 7 EXMC_timing models Timing model Extend mode Mode description Write timing parameter Read timing parameter Async Mode 1 0 SRAM PSRAM CRAM DSET ASET DSET ASET Mode 2 0 NOR Flash DSET ASET DSET ASET Mode A 1 SRAM PSRAM CRAM with EXMC_OE toggling on data phase WDSET WASET DSET ASET Mode B 1 NOR Flas...

Page 690: ...ming patterns for read and write access could be generated independently according to EXMC_SNTCFGx and EXMC_SNWTCFGx register s configuration Asynchronous access timing diagram Mode 1 SRAM CRAM Figure 25 7 Mode 1 read access Address EXMC_A 25 0 Byte Lane Select EXMC_NBL 1 0 Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data EXMC_D 15 0 Memory Output Address Setup Time ASET HCLK...

Page 691: ... to 1 8 SBRSTEN 0x0 7 Reserved 0x1 6 NREN No effect 5 4 NRW Depends on memory 3 2 NRTP Depends on memory except 2 Nor Flash 1 NRMUX 0x0 0 NRBKEN 0x1 EXMC_SNTCFGx 31 30 Reserved 0x0000 29 28 ASYNCMOD No effect 27 24 DLAT No effect 23 20 CKDIV No effect 19 16 BUSLAT Time between EXMC_NE x rising edge to EXMC_NE x falling edge 15 8 DSET Depends on memory and user DSET 1 HCLK for write DSET HCLK for r...

Page 692: ... 0 Address Setup Time ASET HCLK Data Setup Time DSET HCLK EXMC Output 1 HCLK The different between mode A and mode 1 write timing is that read write timing is specified by the same set of timing configuration while mode A write timing configuration is independent of its read configuration Table 25 9 Mode A related registers configuration EXMC_SNCTLx Bit Position Bit Name Reference Setting Value 31...

Page 693: ...ry and user DSET 1 HCLK for write DSET HCLK for read 7 4 AHLD No effect 3 0 ASET Depends on memory and user EXMC_SNWTCFGx Write 31 30 Reserved 0x0 29 28 WASYNCMOD 0x0 27 24 DLAT No effect 23 20 CKDIV No effect 19 16 Reserved 0x00 15 8 WDSET Depends on memory and user 7 4 WAHLD 0x0 3 0 WASET Depends on memory and user Mode 2 B NOR Flash Figure 25 11 Mode 2 B read access Address EXMC_A 25 0 Address ...

Page 694: ...Enable EXMC_NOE Write Enable EXMC_NWE Data EXMC_D 15 0 Address Setup Time WASET HCLK Data Setup Time WDSET HCLK EXMC Output 1 HCLK Table 25 10 Mode 2 B related registers configuration EXMC_SNCTLx Mode 2 Mode B Bit Position Bit Name Reference Setting Value 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 Reserved 0x0 15 ASYNCWTEN Depends on memory 14 EXMODEN Mode 2 0x0 Mode B 0x1 13 NRWTEN 0x0 12 WEN Depen...

Page 695: ...AHLD 0x0 3 0 ASET Depends on memory and user EXMC_SNWTCFGx Write in mode B 31 30 Reserved 0x0000 29 28 WASYNCMOD Mode B 0x1 27 24 DLAT No effect 23 20 CKDIV No effect 19 16 Reserved 0x000 15 8 WDSET Depends on memory and user 7 4 WAHLD 0x0 3 0 WASET Depends on memory and user Mode C NOR Flash OE toggling Figure 25 14 Mode C read access Address EXMC_A 25 0 Address Valid EXMC_NADV Chip Enable EXMC_N...

Page 696: ... is independent of its read configuration Table 25 11 Mode C related registers configuration EXMC_SNCTLx Bit Position Bit Name Reference Setting Value 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 Reserved 0x0 15 ASYNCWTEN Depends on memory 14 EXMODEN 0x1 13 NRWTEN 0x0 12 WEN Depends on user 11 NRWTCFG No effect 10 WRAPEN 0x0 9 NRWTPOL Meaningful only when the bit 15 is set to 1 8 SBRSTEN 0x0 7 Reserve...

Page 697: ...Figure 25 16 Mode D read access Address EXMC_A 25 0 Address Valid EXMC_NADV Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data EXMC_D 15 0 Memory Output Address Setup Time ASET HCLK Data Setup Time DSET HCLK Address Hold Time AHLD HCLK Figure 25 17 Mode D write access Address EXMC_A 25 0 Address Valid EXMC_NADV Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE D...

Page 698: ...memory 1 NRMUX 0x0 0 NRBKEN 0x1 EXMC_SNTCFGx 31 30 Reserved 0x0 29 28 ASYNCMOD Mode D 0x3 27 24 DLAT Don t care 23 20 CKDIV No effect 19 16 BUSLAT Time between EXMC_NE x rising edge to EXMC_NE x falling edge 15 8 DSET Depends on memory and user 7 4 AHLD Depends on memory and user 3 0 ASET Depends on memory and user EXMC_SNWTCFGx 31 30 Reserved 0x0 29 28 WASYNCMOD Mode D 0x3 27 24 DLAT Don t care 2...

Page 699: ...able EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data EXMC_D 15 0 Address Setup Time ASET HCLK Data Setup Time DSET HCLK 1 HCLK Address Hold Time AHLD HCLK Address 15 0 Address 25 16 EXMC output Table 25 13 Multiplex mode related registers configuration EXMC_SNCTLx Bit Position Bit Name Reference Setting Value 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 Reserved 0x0 15 ASYNCWTEN Depends on ...

Page 700: ...t timing of asynchronous communication Wait feature is controlled by the bit ASYNCWAIT in register EXMC_SNCTLx During extern memory access data setup phase will be automatically extended by the active EXMC_NWAIT signal if ASYNCWAIT bit is set The extend time is calculated as follows 1 If memory wait signal is aligned to EXMC_NOE EXMC_NWE TDATA_SETUP max TWAIT_ASSERTION 4HCLK 2 If memory wait signa...

Page 701: ... Output 1 HCLK Wait EXMC_NWAIT NRWTPOL 1 Synchronous access timing diagram The relation between memory clock EXMC_CLK and system clock HCLK is as follows EXMC_CLK HCLK CKDIV 1 CKDIV is the synchronous clock divider ratio it is configured through the CKDIV control field in the EXMC_SNTCFGx register 1 Data latency and NOR Flash latency Data latency is the number of EXMC_CLK cycles to wait before sam...

Page 702: ... high NRWTPOL 0 valid level of EXMC_NWAIT signal is low In synchronous burst mode EXMC_NWAIT signal has two kinds of configurations NRWTCFG 1 When EXMC_NWAIT signal is active current cycle data is not valid NRWTCFG 0 When EXMC_NWAIT signal is active the next cycle data is not valid It is the default state after reset During wait state inserted via the EXMC_NWAIT signal the controller continues to ...

Page 703: ...urations of synchronous multiplexed read mode EXMC_SNCTLx Bit Position Bit Name Reference Setting Value 31 20 Reserved 0x000 19 SYNCWR No effect 18 16 Reserved 0x0 15 ASYNCWTEN 0x0 14 EXMODEN 0x0 13 NRWTEN Depends on memory 12 WEN No effect 11 NRWTCFG Depends on memory 10 WRAPEN 0x0 9 NRWTPOL Depends on memory 8 SBRSTEN 0x1 burst read enable 7 Reserved 0x1 6 NREN Depends on memory 5 4 NRW 0x1 3 2 ...

Page 704: ...C_NWAIT Data EXMC_D 15 0 Address 15 0 Data Latency DATLAT 2 EXMC_CLK Wait Cycle NRWTCFG 0 Address 25 16 EXMC Data 1 EXMC Data 2 EXMC Data 3 Burst write of three half words Table 25 15 Timing configurations of synchronous multiplexed write mode EXMC_SNCTLx Bit Position Bit Name Reference Setting Value 31 20 Reserved 0x000 19 SYNCWR 0x1 synchronous write enable 18 16 Reserved 0x0 15 AYSNCWAIT 0x0 14...

Page 705: ... IO 1 EXMC_D 2 IO X Data IO 2 EXMC_D 3 IO X Data IO 3 1 Controller initialization In the beginning users should program the SPI initialization register EXMC_SINIT Data sampling clock edge is selected via the POL bit read device ID length could be configured by the IDL bit address bit number is controlled by the ADRBIT and command bit number is set by CMDBIT 2 Read Write operation Three modes of me...

Page 706: ... written through the data output line while read in through the input line The following SPI PSRAM waveforms are configured with SADRBIT 4 0 24 CMDBIT 1 0 1 Figure 25 24 SPI PSRAM access Data EXMC_D 0 Data EXMC_D 1 Clock EXMC_CLK Chip Enable EXMC_NEx Command Data Output 1 Data Output 2 Data Input 1 Data Input 2 4 8 or 16 bit wide 1 26 bit wide 8 bit wide 8 bit wide Address 5 SQPI PSRAM access timi...

Page 707: ...waveforms are configured with ADRBIT 4 0 24 CMDBIT 1 0 1 Figure 25 26 QPI PSRAM access Data EXMC_D 0 Data EXMC_D 1 Clock EXMC_CLK Chip Enable EXMC_NEx Data EXMC_D 2 Data EXMC_D 3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Command Address Data 1 Data 2 Wait 0 1 2 3 4 5 6 7 25 3 5 NAND flash or PC card controller EXMC has partitioned Bank1 and Bank2...

Page 708: ... for 16 bit I O space data transmission width Must be shorted to GND EXMC_NIORD Output I O space output enable EXMC_NIOWR Output I O space write enable EXMC_NREG Output Register signal indicating if access is in Common space or Attribute space EXMC_D 15 0 Input Output Bidirectional data bus EXMC_NCE3_x Output Chip select x 0 1 EXMC_NOE Output Output enable EXMC_NWE Output Write enable EXMC_NWAIT I...

Page 709: ...r PC card programmable parameters Programmable parameter W R Unit Functional description NAND Flash PC Card Min Max High impedance time of the memory data bus HIZ W R HCLK Time to keep the data bus high impedance after starting write operation 0 255 Memory hold time HLD W R HCLK The number of HCLK clock cycles to keep address valid after sending the command In write mode it is also data hold time ...

Page 710: ...MC_CLE EXMC_A 16 becomes valid high level data on the I O pins is regarded as a command by NAND Flash 3 Send the start address of read operation to the common space During the valid period of EXMC_NCE and EXMC_NWE when EXMC_ALE EXMC_A 17 becomes valid high level the data on the I O pins is regarded as an address by NAND Flash 4 Waiting for NAND ready signal In this period NAND controller will main...

Page 711: ...Flash waits for EXMC_INTx signal to be busy and the time period of ATTHLD should be greater than tWB tWB is defined as the time from EXMC_NWE high to EXMC_INTx low For NCE sensitive NAND Flash after the first command byte following address bytes has been entered EXMC_NCE must remain low until EXMC_INTx goes from low to high The ATTHLD value of attribute space can be set in EXMC_NPATCFGx register t...

Page 712: ... 1 is the chip enable signal it indicates whether 8 or 16 bit access operation is being performed EXMC_NWE and EXMC_NOE dictates whether the on going operation is a write or read operation and EXMC_NREG is low during attribute space access IO space EXMC_NCE3_x x 0 1 is the chip enable signal it indicates whether 8 or 16 bit access operation is being performed EXMC_NIOWR and EXMC_NIORD dictates whe...

Page 713: ... and byte access Independent Chip Select control for each memory device Independent configuration for each memory device Write enable and byte lane select outputs Automatic row and bank boundary management Multi device Ping Pong access SDRAM clock configured as fHCLK 2 or fHCLK 3 Programmable timing parameters Automatic Refresh operation with programmable Refresh rate SDRAM power up initialization...

Page 714: ...ernal counter In auto refresh mode refresh command is provided by the EXMC this is necessary because SDRAM must maintain the stored information during an on going transaction refresh commands are issued periodically on the data bus timed by ARINTV bits in EXMC_SDARI register the number of consecutive refresh needed is configured through NARF bits in EXMC_SDCMD register Refresh command always take ...

Page 715: ...q ack_ok rw_req rw_ok SIGNAL GENERATOR SDNE 1 0 D 31 0 NBL 3 0 AHBS_IF_MEM WADDR FIFO WDATA FIFO RADDR FIFO RDATA FIFO REFRESH TIMER AHBS_IF_REG SDRAMC REGS cm_req COMMAND TIMERS EXTERNAL SDRAM COMMAND MODE FSM cm_ok command mode request ADDRESS DECODE ref_req ref_ok SDCK GENERATOR The Signal Generator handles requests from Command mode FSM Refresh Timer and the RW split module The command timers ...

Page 716: ...ry clock EXMC_SDCKE 0 O Clock enable for SDRAM memory 0 EXMC_SDCKE 1 O Clock enable for SDRAM memory 1 EXMC_SDNE 0 O Chip select for SDRAM memory 0 active low EXMC_SDNE 1 O Chip select for SDRAM memory 1 active low EXMC_NRAS O Row address strobe active low EXMC_NCAS O Column address strobe active low EXMC_SDNWE O Write enable active low EXMC_A 12 0 O Address EXMC_A 15 14 O Bank address EXMC_D 31 0...

Page 717: ... register configuration Mode register is programed by writing the mode register content in MRC bits in EXMC_SDCMD register mode register specifies the operating mode of SDRAM such modes include burst length burst type CAS latency and write mode Users should refer to the SDRAM s specification for correct configuration CAS latency should be the same as the CL bits in EXMC_SDCTLx register and burst l...

Page 718: ...er to perform consecutive read access If the next read location is in the same row or another active row read access is proceeded without interruption else a precharge command is issued to deactivate the current row followed by the activation of the row where the next read access is targeted and then the read access is performed A read FIFO is design to cache the read data during CAS latency and p...

Page 719: ...ing diagram shows how delay chain is added Figure 25 31 Data sampling clock delay chain Delay Cell 2 Delay Cell 0 Delay Cell 1 Delay Cell 15 1 HCLK Delay SDSC SSCR RSEN Data Input Sample Clock HCLK SDRAMC can translate AHB single and burst write operation into single memory access Write protection must be disabled by resetting WPEN bit in EXMC_SDCTLx register SDRAMC always keeps track of the activ...

Page 720: ...BRSTRD bit of EXMC_SDCTL0 register is set the RW split module can anticipate the next read access The read FIFOs are used to store data read in advance during the CAS latency period configured by the CL bits of EXMC_SDCTLx and during the PIPED delay configured by the PIPED bits of EXMC_SDCTL0 The RDATA FIFO can buffers up to 6 32 bit read data words while the RADDR FIFO carries 6 14 bit read addre...

Page 721: ...translate the address of the AHB bus address to chip select internal bank address row address and column address according to the configuration of external memory device The active cache sub module records whether the internal banks up to 8 are in the active state When an internal bank is in active state the corresponding row address is also recorded When an AHB access or an auto refresh command i...

Page 722: ...ess Strobe EXMC_NRAS Write Enable EXMC_SDNWE Data EXMC_D 31 0 Clock EXMC_SDCLK Address EXMC_A 12 0 Col m Col m 1 Row n 1 Col m Col m 1 Col m 2 Col m Col m 1 Col m Col m 1 Col m 2 RPD 3 RCD 3 CL 3 Precharge Active Row Read Command Row n Figure 25 36 Cross boundary write operation Chip Enable EXMC_SDNEx Column Address Strobe EXMC_NCAS Row Address Strobe EXMC_NRAS Write Enable EXMC_SDNWE Data EXMC_D ...

Page 723: ...delay if this command is issued to both SDRAM devices or one of the SDRAM device is not initialized 2 Power down mode In power down mode refresh is provided by the SDRAM controller It is entered by writing 0b110 to CMD bits in EXMC_SDCMD register DS0 and DS1 determines which SDRAM device will receive the command If the write data FIFO is not empty all data are sent to the memory before activating ...

Page 724: ...RAMC s internal register is sent Device0 and Device1 status bits STA0 and STA1 in EXMC_SDSTAT register defines the status of SDRAM deivce0 and device1 respectively 0b00 represents normal mode 0b01 indicates that the corresponding SDRAM devices is in self refresh mode and 0b10 signifies the power down mode If a new refresh request occurs while the previous refresh command has not been served yet a ...

Page 725: ...NRWT EN WREN NRWT CFG WRAPEN NRWT POL SBR STEN Reserved NR EN NRW 1 0 NRTP 1 0 NR MUX NRBK EN rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 SYNCWR Synchronous write 0 Asynchronous write 1 Synchronous write 18 16 Reserved Must be kept at reset value 15 ASYNCWAIT Asynchronous wait 0 Disable the asynchronous wait feature 1 Enable the asy...

Page 726: ...Synchronous burst enable 0 Disable burst access mode 1 Enable burst access mode 7 Reserved Must be kept at reset value 6 NREN NOR Flash access enable 0 Disable NOR Flash access 1 Enable NOR Flash access 5 4 NRW 1 0 NOR bank memory data bus width 00 8 bits 01 16 bits default after reset 10 11 Reserved 3 2 NRTP 1 0 NOR bank memory type 00 SRAM ROM 01 PSRAM CRAM 10 NOR Flash 11 Reserved 1 NRMUX NOR b...

Page 727: ...0x0 Data latency of first burst access is 2 CLK 0x1 Data latency of first burst access is 3 CLK 0xF Data latency of first burst access is 17 CLK 23 20 CKDIV 3 0 Synchronous clock divide ratio This filed is only effect in synchronous mode 0x0 Reserved 0x1 EXMC_CLK period 2 HCLK period 0xF EXMC_CLK period 16 HCLK period 19 16 BUSLAT 3 0 Bus latency The bits are defined in multiplexed read mode in or...

Page 728: ... meaningful only when the EXMODEN bit in EXMC_SNCTLx is set to 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved WASYNCMOD 1 0 DLAT 3 0 CKDIV 3 0 Reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDSET 7 0 WAHLD 3 0 WASET 3 0 rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 28 WASYNCMOD 1 0 Asynchronous a...

Page 729: ... mode 0x0 Reserved 0x1 Address hold time 2 HCLK 0xF Address hold time 16 HCLK 3 0 WASET 3 0 Address setup time This field is used to set the time of address setup phase Note Meaningful only in asynchronous access of SRAM ROM NOR Flash 0x0 Address setup time 1 HCLK 0x1 Address setup time 2 HCLK 0xF Address setup time 16 HCLK 25 4 2 NAND flash PC card controller registers NAND flash PC card control ...

Page 730: ... delay 2 HCLK 0xF CLE to RE delay 16 HCLK 8 7 Reserved Must be kept at reset value 6 ECCEN ECC enable 0 Disable ECC and reset EXMC_NECCx 1 Enable ECC 5 4 NDW 1 0 NAND bank memory data bus width 00 8 bits 01 16 bits Others Reserved Note for PC CF card 16 bit bus width must be selected 3 NDTP NAND bank memory type 0 PC Card CF card PCMCIA 1 NAND Flash 2 NDBKEN NAND bank enable 0 Disable correspondin...

Page 731: ...mpty 1 FIFO is empty 5 INTFEN Interrupt falling edge detection enable 0 Disable interrupt falling edge detection 1 Enable interrupt falling edge detection 4 INTHEN Interrupt high level detection enable 0 Disable interrupt high level detection 1 Enable interrupt high level detection 3 INTREN Interrupt rising edge detection enable bit 0 Disable interrupt rising edge detection 1 Enable interrupt risi...

Page 732: ...its are defined as time of bus keep high impedance state after writing the data 0x00 COMHIZ 1 HCLK 0xFE COMHIZ 255 HCLK 0xFF COMHIZ 256 HCLK 23 16 COMHLD 7 0 Common memory hold time After sending the address the bits are defined as the address hold time In write operation they are also defined as the data signal hold time 0x00 Reserved 0x01 COMHLD 1 HCLK 0xFE COMHLD 254 HCLK 0xFF COMHLD 255 HCLK 1...

Page 733: ...12 11 10 9 8 7 6 5 4 3 2 1 0 ATTWAIT 7 0 ATTSET 7 0 rw rw Bits Fields Description 31 24 ATTHIZ 7 0 Attribute memory data bus HiZ time The bits are defined as time of bus keep high impedance state after writing the data 0x00 ATTHIZ 1 HCLK 0xFE ATTHIZ 255 HCLK 0xFF ATTHIZ 256 HCLK 23 16 ATTHLD 7 0 Attribute memory hold time After sending the address the bits are defined as the address hold time In w...

Page 734: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IOWAIT 7 0 IOSET 7 0 rw rw Bits Fields Description 31 24 IOHIZ 7 0 IO space data bus HiZ time The bits are defined as time of bus keep high impedance state after writing the data 0x00 IOHIZ 0 HCLK 0xFF IOHIZ 255 HCLK 23 16 IOHLD 7 0 IO space hold time After sending the address the bits are defined as the address hold time In write operation they are also defin...

Page 735: ... 21 20 19 18 17 16 ECC 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ECC 15 0 r Bits Fields Description 31 0 ECC 31 0 ECC result ECCSZ 2 0 NAND Flash page size ECC bits 0b000 256 ECC 21 0 0b001 512 ECC 23 0 0b010 1024 ECC 25 0 0b011 2048 ECC 27 0 0b100 4096 ECC 29 0 0b101 8192 ECC 31 0 25 4 3 SDRAM controller registers SDRAM control registers EXMC_SDCTLx x 0 1 Address offset 0x140 0x04 x x 0 1 Res...

Page 736: ...bled Note The corresponding bits in the EXMC_SDCTL1 register are reserved 11 10 SDCLK 1 0 SDRAM clock configuration These bits specifies the SDRAM clock period for both SDRAM devices The memory clock should be disabled before change and the SDRAM memory must be re initialized after this configuration is changed 00 SDCLK memory clock disabled 01 Reserved 10 SDCLK memory period 2 x HCLK periods 11 S...

Page 737: ...s 01 9 bits 10 10 bits 11 11 bits SDRAM timing configuration registers EXMC_SDTCFGx x 0 1 Address offset 0x148 0x04 x x 0 1 Reset value 0x0FFF FFFF This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RCD 3 0 RPD 3 0 WRD 3 0 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARFD 3 0 RASD 3 0 XSRD 3 0 LMRD 3 0 rw rw rw rw Bits Fields Descriptions 31 ...

Page 738: ...es are used the WRD must be programmed with the timings of the slower one 15 12 ARFD 3 0 Auto refresh delay These bits specify the delay between two consecutive Refresh commands the delay between two Activate commands as well as the delay between the Refresh command and the Activate command in SDRAM memory clock cycle unit 0x0 1 cycle 0x1 2 cycles 0xF 16 cycles Note The corresponding bits in the E...

Page 739: ... 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MRC 12 7 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MRC 6 0 NARF 3 0 DS0 DS1 CMD 2 0 rw rw rw rw rw Bits Fields Descriptions 31 22 Reserved Must be kept at reset value 21 9 MRC 12 0 Mode register content These bits specify the SDRAM Mode Register content which will be programmed when...

Page 740: ...down entry command 111 Reserved Note At least one command device select bit DS1 orDS0 must be set when a command is issued If both devices are used the commands must be issued to the two devices by setting the DS1and DS0 bits at the same time SDRAM auto refresh interval register EXMC_SDARI Address offset 0x154 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 2...

Page 741: ...21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NRDY STA1 1 0 STA0 1 0 REIF r r r r Bits Fields Descriptions 31 6 Reserved Must be kept at reset value 5 NRDY Not Ready status This bit specifies whether the SDRAM controller is ready for a new command 0 SDRAM Controller is ready for a new command 1 SDRAM Controller is not ready for a new command 4 3 STA1 1 0 Device1 status ...

Page 742: ...ample clock of read data 0x0 Select the clock after 0 delay cell 0x1 Select the clock after 1 delay cell 0xF Select the clock after 15 delay cell 3 2 Reserved Must be kept at reset value 1 SSCR Select sample cycle of read data 0 add 0 extra HCLK cycle to the read data sample clock besides the delay chain 1 add 1 extra HCLK cycle to the read data sample clock besides the delay chain 0 RSEN Read sam...

Page 743: ... of SPI PSRAM address phase Value Range 1 to 26 default 24 0x00 reserved 0x01 1 bit address 0x1A 26 bit address 0x1B reserved 0x1F reserved 23 18 Reserved Must be kept at reset value 17 16 CMDBIT 1 0 Bit number of SPI PSRAM command phase 00 4 bit 01 8 bit default 10 16 bit 11 Reserved 15 0 Reserved Must be kept at reset value SPI read command register EXMC_SRCMD Offset address 0x320 Reset Value 0x...

Page 744: ...nt valid RCMD is different CMDBIT 00 RCMD 3 0 are valid CMDBIT 01 RCMD 7 0 are valid CMDBIT 10 RCMD 15 0 are valid Note Before writing 1 to RDID bit users must ensure it is cleared by reading RDID as 0 SPI write command register EXMC_SWCMD Offset address 0x330 Reset Value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SC Reserved WMODE 1...

Page 745: ...x340 Reset Value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIDL 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIDL 15 0 rw Bits Fields Descriptions 31 0 SIDL 31 0 ID Low Data saved for SPI Read ID Command SIDL 31 0 is valid when IDL 01 or 00 SIDL 15 0 is valid when IDL 10 SIDL 7 0 is valid when IDL 11 SPI ID high register EXMC_SIDH...

Page 746: ...GD32F20x User Manual 746 rw Bits Fields Descriptions 31 0 SIDH 63 32 ID High Data saved for SPI Read ID Command Note SIDH 31 0 is valid when IDL 00 ...

Page 747: ...ages The transmission scheduler decides which mailbox has to be transmitted first Three complete messages can be stored in each FIFO The FIFOs are managed completely by hardware Two receive FIFOs are used by hardware to store the incoming messages The CAN controller also provides all hardware functions for supporting the time triggered communication option for safety critical applications 26 2 Cha...

Page 748: ...s Sleep working mode Initial working mode Normal working mode Sleep working mode Sleep working mode is the default mode after reset In sleep working mode the CAN is in the low power status while the CAN clock is stopped When SLPWMOD bit in CAN_CTL register is set the CAN enters the sleep working mode Then the SLPWS bit in CAN_STAT register is set To leave sleep working mode automatically the AWU b...

Page 749: ...D and SLPWMOD bit in CAN_ CTL register Normal working mode to Sleep working mode Set SLPWMOD bit in CAN_CTL register and wait the current transmission or reception completed Normal working mode to Initial working mode Set IWMOD bit in CAN_CTL register and wait the current transmission or reception completed 26 3 2 Communication modes The CAN interface has four communication modes Silent communicat...

Page 750: ... bit in CAN_BT register to enter loopback and silent communication mode or clear them to leave Loopback and silent communication mode is useful on self test The TX pin holds logical one The RX pin holds high impedance state Normal communication mode Normal communication mode is the default communication mode unless the LCMOD or SCMOD bit in CAN_BT register is set 26 3 3 Data transmission Transmiss...

Page 751: ...shed Typically MTF is set when the frame in the transmit mailbox has been sent MTFNERR mailbox transmits finished and no error MTFNERR is set when the frame in the transmission mailbox has been sent without any error MAL mailbox arbitration lost MAL is set while the frame transmission is failed because of the arbitration lost MTE mailbox transmits error MTE is set while the frame transmission is f...

Page 752: ...rst 26 3 4 Data reception Reception register Two receive FIFOs are transparent to the application You can use receive FIFOs through five registers CAN_RFIFOx CAN_RFIFOMIx CAN_RFIFOMPx CAN_RFIFOMDATA0x and CAN_RFIFOMDATA1x FIFO s status and operation can be handled by CAN_RFIFOx register Reception frame data can be achieved through the registers CAN_RFIFOMIx CAN_RFIFOMPx CAN_RFIFOMDATA0x and CAN_RF...

Page 753: ...gister is reset the new frame is stored into the receive FIFO and the last frame in the receive FIFO is discarded Steps of receiving a message Step 1 Check the number of frames in the receive FIFO Step 2 Reading CAN_RFIFOMIx CAN_RFIFOMPx CAN_RFIFOMDATA0x and CAN_RFIFOMDATA1x if there is data pending Step 3 Set the RFDx bit in CAN_RFIFOx register 26 3 5 Filtering function The CAN would receive fram...

Page 754: ...T FF EFID 17 15 FDATA0 31 21 FDATA0 20 16 FDATA1 31 21 FDATA1 20 16 ID Mask List mode The filter consists of frame identifiers The filter can decide whether a frame will be discarded or not When one frame arrived the filter will check which member can match the identifier of the frame 32 bit list mode example is shown in Figure 26 9 32 bit list mode filter Figure 26 9 32 bit list mode filter FDATA...

Page 755: ...asses the filters a filter number must associate with the frame The filter number is called filtering index It stores in the FI bits in CAN_RFIFOMPx when the frame is read by the application Each FIFO numbers the filters within the banks associated with the FIFO itself whether the bank is active or not The example about filtering index is shown in Table 26 2 Filtering index Table 26 2 Filtering in...

Page 756: ...11 F9DATA0 32 16 16bit Mask F11DATA0 32 16 16bit Mask 12 F9DATA1 15 0 16bit ID 14 F11DATA1 15 0 16bit ID 13 F9DATA1 32 16 16bit Mask F11DATA1 32 16 16bit Mask 14 12 F12DATA0 32bit ID Yes 15 13 F13DATA0 32bit ID Yes 15 F12DATA1 32bit Mask F13DATA1 32bit Mask 16 Priority The filters have the priority 1 32 bit mode is higher than 16 bit mode 2 List mode is higher than mask mode 3 Smaller filter index...

Page 757: ... CAN_TSTAT register by the MTFNERR MAL and MTE bits Bit time On the bit level the CAN protocol uses synchronous bit transmission This not only enhances the transmitting capacity but also means that a sophisticated method of bit synchronization is required While bit synchronization in a character oriented transmission asynchronous is performed upon the reception of the start bit available with each...

Page 758: ...y segment Phase buffer segment 1 Phase buffer segment2 Normal Bit Time CAN protocol SYNG_SEG BIT SEGMENT 1 BS1 BIT SEGMENT 2 BS2 CAN The resynchronization Jump Width SJW defines an upper bound to the amount of lengthening or shortening of the bit segments It is programmable between 1 and 4 time quanta A valid edge is defined as the first transition in a bit time from dominant to recessive bus leve...

Page 759: ...er than 255 This state is indicated by BOERR bit in CAN_ERR register In Bus Off state the CAN is no longer able to transmit and receive messages Depending on the ABOR bit in the CAN_CTL register CAN will recover from Bus Off becomes error active again either automatically or on software request But in both cases the CAN has to wait at least for the recovery sequence specified in the CAN standard 1...

Page 760: ...egister is set and RFOIE0 in CAN_INTEN register is set Receive FIFO1 interrupt The Receive FIFO1 interrupt can be generated by the following conditions Reception FIFO1 not empty RFL1 bits in the CAN_RFIFO1 register are not 00 and RFNEIE1 in CAN_INTEN register is set Reception FIFO1 full RFF1 bit in the CAN_RFIFO1 register is set and RFFIE1 in CAN_INTEN register is set Reception FIFO1 overrun RFO1 ...

Page 761: ...for debug or works normal If the CANx_HOLD in DBG_CTL0 register is cleared this bit takes no effect 0 CAN reception and transmission works normal even during debug 1 CAN reception and transmission stops working during debug 15 SWRST Software reset 0 No effect 1 Reset CAN with working mode of sleep This bit is automatically reset to 0 14 8 Reserved Must be kept at reset value 7 TTC Time triggered c...

Page 762: ...king mode If this bit is set by software the CAN enters sleep working mode after the current transmission or reception completed This bit can cleared by software or hardware If AWU bit in CAN_CTL register is set this bit is cleared by hardware when CAN bus activity detected 0 Disable sleep working mode 1 Enable sleep working mode 0 IWMOD Initial working mode 0 Disable initial working mode 1 Enable...

Page 763: ...bit in CAN_ERR register is set and BOIE bit in CAN_INTEN register is set Or the PERR bit in CAN_ERR register is set and PERRIE bit in CAN_INTEN register is set Or the WERR bit in CAN_ERR register is set and WERRIE bit in CAN_INTEN register is set Or the ERRN bits in CAN_ERR register are set to 1 to 6 not 0 and not 7 and ERRNIE in CAN_INTEN register is set This bit is cleared by software when writi...

Page 764: ...UM 1 0 MST2 Reserved MTE2 MAL2 MTFNERR2 MTF2 r r r r r r r rs rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MST1 Reserved MTE1 MAL1 MTFNERR1 MTF1 MST0 Reserved MTE0 MAL0 MTFNERR0 MTF0 rs rc_w1 rc_w1 rc_w1 rc_w1 rs rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 TMLS2 Transmit mailbox 2 last sending in transmit FIFO This bit is set by hardware when transmit mailbox 2 has the las...

Page 765: ... MTF2 bit in CAN_TSTAT register This bit is reset by hardware when next transmission starts 17 MTFNERR2 Mailbox 2 transmit finished and no error This bit is set when the transmission finished and no error This bit is reset by software when writing 1 to this bit or MTF2 bit in CAN_TSTAT register This bit is reset by hardware when the transmission finished with error 0 Mailbox 2 transmit finished wi...

Page 766: ...ardware while the mailbox 0 is empty 6 4 Reserved Must be kept at reset value 3 MTE0 Mailbox 0 transmit error This bit is set by hardware while the transmit error is occurred This bit reset by software when write 1 to this bit or MTF0 bit in CAN_TSTAT register This bit reset by hardware when next transmission starts 2 MAL0 Mailbox 0 arbitration lost This bit is set while the arbitration lost is oc...

Page 767: ...the dequeuing is done 4 RFO0 Receive FIFO0 overfull This bit is set by hardware when receive FIFO0 is overfull and reset by software when writing 1 to this bit 0 The receive FIFO0 is not overfull 1 The receive FIFO0 is overfull 3 RFF0 Receive FIFO0 full This bit is set by hardware when receive FIFO0 is full and reset by software when writing 1 to this bit 0 The receive FIFO0 is not full 1 The rece...

Page 768: ...O1 full This bit is set by hardware when receive FIFO1 is full and reset by software when write 1 to this bit 0 The receive FIFO1 is not full 1 The receive FIFO1 is full 2 Reserved Must be kept at reset value 1 0 RFL1 1 0 Receive FIFO1 length These bits are the length of the receive FIFO1 26 4 6 Interrupt enable register CAN_INTEN Address offset 0x14 Reset value 0x0000 0000 This register has to be...

Page 769: ...ble 8 WERRIE Warning error interrupt enable 0 Warning error interrupt disable 1 Warning error interrupt enable 7 Reserved Must be kept at reset value 6 RFOIE1 Receive FIFO1 overfull interrupt enable 0 Receive FIFO1 overfull interrupt disable 1 Receive FIFO1 overfull interrupt enable 5 RFFIE1 Receive FIFO1 full interrupt enable 0 Receive FIFO1 full interrupt disable 1 Receive FIFO1 full interrupt e...

Page 770: ... rw r r r Bits Fields Descriptions 31 24 RECNT 7 0 Receive Error Count defined by the CAN standard 23 16 TECNT 7 0 Transmit Error Count defined by the CAN standard 15 7 Reserved Must be kept at reset value 6 4 ERRN 2 0 Error number These bits indicate the error status of bit transformation They are updated by the hardware While the bit transformation is successful they are equal to 0 Software can ...

Page 771: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BAUDPSC 9 0 rw Bits Fields Descriptions 31 SCMOD Silent communication mode 0 Silent communication disable 1 Silent communication enable 30 LCMOD Loopback communication mode 0 Loopback communication disable 1 Loopback communication enable 29 26 Reserved Must be kept at reset value 25 24 SJW 1 0 Resynchronization jump width Resynchronization jump width time...

Page 772: ...ormat frame identifier 20 16 EFID 17 13 The frame identifier EFID 17 13 Extended format frame identifier 15 3 EFID 12 0 The frame identifier EFID 12 0 Extended format frame identifier 2 FF Frame format 0 Standard format frame 1 Extended format frame 1 FT Frame type 0 Data frame 1 Remote frame 0 TEN Transmit enable This bit is set by the software when one frame will be transmitted and reset by the ...

Page 773: ...s available while the TTC bit in CAN_CTL is set 7 4 Reserved Must be kept at reset value 3 0 DLENC 3 0 Data length code DLENC 3 0 is the number of bytes in a frame 26 4 11 Transmit mailbox data0 register CAN_TMDATA0x x 0 2 Address offset 0x188 0x198 0x1A8 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB3 7 0 DB2 7 0 rw rw 15...

Page 774: ... 7 0 DB4 7 0 Data byte 4 26 4 13 Receive FIFO mailbox identifier register CAN_RFIFOMIx x 0 1 Address offset 0x1B0 0x1C0 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SFID 10 0 EFID 28 18 EFID 17 13 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFID 12 0 FF FT Reserved r r r Bits Fields Descriptions 31 21 SFID 10 0 EFID 28 18 The...

Page 775: ...1 20 19 18 17 16 TS 15 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FI 7 0 Reserved DLENC 3 0 r r Bits Fields Descriptions 31 16 TS 15 0 Time stamp The time stamp of frame in transmit mailbox 15 8 FI 7 0 Filtering index The index of the filter by which the frame is passed 7 4 Reserved Must be kept at reset value 3 0 DLENC 3 0 Data length code DLENC 3 0 is the number of bytes in a frame 26 4 15 Receiv...

Page 776: ...et value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB7 7 0 DB6 7 0 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DB5 7 0 DB4 7 0 r r Bits Fields Descriptions 31 24 DB7 7 0 Data byte 7 23 16 DB6 7 0 Data byte 6 15 8 DB5 7 0 Data byte 5 7 0 DB4 7 0 Data byte 4 26 4 17 Filter control register CAN_FCTL Address offset 0x200 Reset value 0x2A1...

Page 777: ...00 0000 This register has to be accessed by word 32 bit This register can be modified only when FLD bit in CAN_FCTL register is set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FMOD27 FMOD26 FMOD25 FMOD24 FMOD23 FMOD22 FMOD21 FMOD20 FMOD19 FMOD18 FMOD17 FMOD16 rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMOD15 FMOD14 FMOD13 FMOD12 FMOD11 FMOD10 FMOD9 FMOD8...

Page 778: ...000 This register has to be accessed by word 32 bit This register can be modified only when FLD bit in CAN_FCTL register is set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FAF27 FAF26 FAF25 FAF24 FAF23 FAF22 FAF21 FAF20 FAF19 FAF18 FAF17 FAF16 rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FAF15 FAF14 FAF13 FAF12 FAF11 FAF10 FAF9 FAF8 FAF7 FAF6 FAF5 FAF4 FAF...

Page 779: ... data y register CAN_FxDATAy x 0 27 y 0 1 Address offset 0x240 8 x 4 y x 0 27 y 0 1 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FD31 FD30 FD29 FD28 FD27 FD26 FD25 FD24 FD23 FD22 FD21 FD20 FD19 FD18 FD17 FD16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FD15 FD14 FD13 FD12 FD11 FD10 ...

Page 780: ... receive pause frame after current transmitting frame complete MAC automatically transmits pause frame or back pressure feature depending on fill level of RxFIFO in Full duplex mode or in Half duplex mode Automatic transmission of pause frame on assertion and de assertion of flow control input frame Zero quanta pause time length frame for Full duplex operation IEEE 802 3x flow control for Full dup...

Page 781: ...e deferral or underrun Calculate and insert IPv4 header checksum and TCP UDP or ICMP checksum in frame transmit under Store and Forward mode DMA Feature Two types of descriptor addressing Ring and Chain Each descriptor can transfer up to 8 KB of data Programmable normal and abnormal interrupt for many status conditions Round robin or fixed priority arbitration between reception and transmission co...

Page 782: ...status to memory RxMTL used to control management and store reception data RxFIFO is implemented in this module and used to temporarily store received frame data before forwarding them into the system physical memory The MAC reception relative control registers used to control frame receive and marked the receiving state Also a receiving filter with a variety of filtering mode is implemented in MA...

Page 783: ...iguration MAC signals Pin Pin configuration MII default MII remap RMII default RMII remap ETH_MDC PC1 AF output push pull highspeed 50 MHz MDC MDC ETH_MII_TXD2 PC2 AF output push pull highspeed 50 MHz TXD2 ETH_MII_TX_CLK PC3 Floating input reset state TX_CLK ETH_MII_CRS PA0 Floating input reset state CRS ETH_RX_CLK ETH_RMII_REF_CLK PA1 Floating input reset state RX_CLK REF_CLK Preamble SFD Destina...

Page 784: ...3 ETH_PPS_OUT PB5 AF output push pull highspeed 50 MHz PPS_OUT PPS_OUT ETH_MII_TXD3 PB8 AF output push pull highspeed 50 MHz TXD3 ETH_MII_RX_ER PB10 Floating input reset state RX_ER ETH_MII_TX_EN ETH_RMII_TX_EN PB11 AF output push pull highspeed 50 MHz TX_EN TX_EN ETH_MII_TXD0 ETH_RMII_TXD0 PB12 AF output push pull highspeed 50 MHz TXD0 TXD0 ETH_MII_TXD1 ETH_RMII_TXD1 PB13 AF output push pull high...

Page 785: ... level lasts time of MDC must be 160ns and the minimum period of MDC must be 400ns when it is in data transmission state MDIO Used to transfer data in conjunction with the MDC clock line receiving data from external PHY or sending data to external PHY Figure 27 3 Station management interface signals SMI write operation Applications need to write transmission data to the ENET_MAC_PHY_DATA register ...

Page 786: ...ications Details of catalog that firmware library currently supports the PHY device can refer to firmware library related instructions SMI clock selection The SMI clock is generated by dividing application clock AHB clock In order to guarantee the MDC clock frequency is no more than 2 5MHz application should set appropriate division factor according to the different AHB clock frequency The followi...

Page 787: ...o transition synchronously with respect to the TX and RX clock MII_COL Collision detection signal only working in Half duplex mode controlled by the PHY It is active when a collision on the medium is detected and must it will remain active while the collision condition continues This signal is not required to transition synchronously with respect to the TX and RX clock MII_RXD 3 0 Receive data lin...

Page 788: ...ith MAC clock It can use the external 25MHz crystal or the output clock of microcontroller s CK_OUT0 pin If the clock source is selected from CK_OUT0 pin the MCU needs to configure the appropriate PLL to ensure the output frequency of CK_OUT0 pin is 25MHz RMII Reduced media independent interface The reduced media independent interface RMII specification reduces the pin count during Ethernet commun...

Page 789: ... the appropriate PLL to ensure the output frequency of CK_OUT0 pin is 50MHz 27 3 2 MAC function overview MAC module can achieve the following functions Data package transmission and reception Frame detecting decoding and frame boundary delimitation Addressing handling source address and destination address Error conditions detect Medium access management in Half duplex mode Medium allocation preve...

Page 790: ...hen the transmit FIFO size is smaller than the Ethernet frame to be transmitted the frame is popped towards the MAC when the transmit FIFO becomes almost full Handle special cases In the transmission process due to the insufficient TxDMA descriptor or misuse of FTF bit in ENET_DMA_CTL register when this bit is set it will clear FIFO data and reset the FIFO pointer after clear operation is complete...

Page 791: ...ransmit descriptor along with transmit status Transmit FIFO flush operation Application can clear TxFIFO and reset the FIFO data pointer by setting FTF bit bit 20 of ENET_DMA_CTL register The flush operation will be executed at once no matter whether TxFIFO is popping data to MAC This results in an underflow event in the MAC transmitter and the makes frame transmission abort At the same time MAC r...

Page 792: ...doing this MAC sends a pause frame right now with the pause time value PTM configured in ENET_MAC_FCTL register If application considers the pause time is no need any more because the transmit frame can be transmitted without pause time it can end the pause time by setting the pause time value PTM bits in ENET_MAC_FCTL register to 0 and set FLCB BKPA bit to send this zero pause time frame 2 MAC au...

Page 793: ...d Note This function is enabled only when the TSFD bit in the ENET_DMA_CTL register is set TxFIFO is configured to Store and Forward mode and application must ensure the TxFIFO deep enough to store the whole transmit frame If the depth of the TxFIFO is less than the frame length the MAC only does calculation and insertion for IPv4 header checksum field See IETF specifications RFC 791 RFC 793 RFC 7...

Page 794: ...d will instead the transmission frame s original checksum field by the final calculation results After calculated by checksum offload module the result can be found in IPPE bit bit 12 in TDES0 The following shows the conditions under which the IPPE bit can be set 1 In Store and Forward mode frame has been forwarded to MAC transmitter but no EOF is written to TxFIFO 2 Frame is ended but the byte nu...

Page 795: ...ress 1 to address 3 can be configured to use or not Each byte of MAC address 1 to MAC address 3 register can be masked for comparison with the corresponding destination address byte of received frame by setting the corresponding mask byte bits MB in the corresponding register Hash list filtering In this filter mode MAC uses a HASH mechanism MAC uses a 64 bit hash list to filter the received unicas...

Page 796: ... and SA filter This means that as long as a frame does not pass any one of the filters DA filter or SA filter it will be discarded Only a frame passing the entire filter can be forwarded to the application Reverse filtering operation MAC can reverse filter match result at the final output whether the destination address filtering or source address filtering By setting the DAIFLT and SAIFLT bits in...

Page 797: ...ilter match but do not drop frames that fail 0 1 0 Fail status on perfect group filter match but do not drop frame 0 0 1 Pass on perfect group filter match and drop frames that fail 0 1 1 Fail on perfect group filter match and drop frames that fail Promiscuous mode If the PM bit in ENET_MAC_FRMF register is set promiscuous mode is enable Then the address filter function is bypassed all frames are ...

Page 798: ...d the MAC can extend the max receiving data bytes to 16384 16K Bytes any data beyond this number will be cut off When RxFIFO works at Cut Through mode it starts popping out data from RxFIFO when the number of FIFO is greater than threshold value RTHC bits in ENET_DMA_CTL register After all data of a frame pop out receive status word is sent to DMA for writing back to descriptor In this mode if a f...

Page 799: ... is also used to identify frames with VLAN tags Header checksum error bits in DMA receive descriptor the 7 bit in RDES0 reflects the header checksum result This bit is set if received IP header has the following errors Any mismatch between the IPv4 calculation result by checksum offload module and the value in received frame s checksum field Any inconsistent between the data type of Ethernet type ...

Page 800: ...n check these flags for upper protocol implementation Note The value of frame length is 0 means that for some reason such as FIFO overflow or dynamically modify the filter value in the receiving process resulting did not pass the filter etc frame data is not written to FIFO completely MAC loopback mode Often loopback mode is used for testing and debugging hardware and software system for applicati...

Page 801: ...in ENET_MAC_WUM register the Ethernet enters into power down state In power down state MAC ignores all the frame data on the interface until the power down state is exited For exiting power down state application can choose one or both of the two methods mentioned above Setting WFEN bit in ENET_MAC_WUM register can make Ethernet wakeup if a remote wakeup frame received and setting MPE bit in ENET_...

Page 802: ...ss type selection bit If this bit is 1 the detection only detects a multicast frame and if this bit is 0 the detection only detects a unicast frame Bit 2 and bit 1 must be set to 0 Bit 0 is the filter switch bit Setting it to 1 means enable and 0 means disable Filter n offset It is used in conjunction with filter n byte mask field This register specifies offset within the frame of the first byte w...

Page 803: ...n address 0xAABB CCDD EEFF is the following MISC indicates miscellaneous additional data bytes in the packet DESTINATION SOURCE MISC FF FF FF FF FF FF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF MISC FCS ...

Page 804: ... a wakeup type frame the Ethernet module exits the power down state 10 Reading the ENET_MAC_WUM register to clear the power management event flags Enable MAC s transmit function and enable TxDMA and RxDMA 11 Initialize the MCU system clock enable HXTAL and configure the RCU unit 27 3 5 Precision time protocol PTP The majority of protocols are implemented by the UDP layer application software The P...

Page 805: ...et PTP timestamp update register is used for adjust system time by adding or subtracting If fine correction method is selected operation is different The fine correction method corrects system time not in a single clock cycle The fine correction frequency can be configured by application to make slave clock frequency smoothly adapt master clock without unpredictability large jitter This method is ...

Page 806: ... in order to make the system time accuracy to 20ns sub second increment register value should be set to 20 0 46 0d43 Note The algorithm described below based on constant delay transferred between master and slave devices Master to Slave Delay Synchronous frequency ratio will be confirmed by the algorithm after a few Sync cycles Algorithm is as follows Define the master sends a SYNC message to slav...

Page 807: ...itialize 8 Send initialization command by setting bit 2 in the ENET_PTP_TSCTL register 9 The timestamp counter starts counting as soon as the initialization process complete System time update steps under coarse correction method 1 Program the offset may be negative value in the timestamp update high and low registers 2 Set bit 3 TMSSTU in the ENET_PTP_TSCTL register to update the timestamp regist...

Page 808: ... input of TIMER1 For this feature designed no uncertainty is introduced because the clock of the TIMER1 and PTP reference clock HCLK are synchronous PTP pulse per second PPS output signal Application configures ETH_PPS_OUT pin to AF output push pull to enable the PPS output function This function can output a signal with the pulse width of 125ms which can be used to check the synchronization betwe...

Page 809: ... should be all stored the data buffer address this connection method of descriptor table is called ring structure When current descriptor s buffer address is used descriptor pointer will point to the next descriptor If chain structure is selected the pointer points to the value of buffer 2 If ring structure is selected the pointer points to an address calculated as below Next descriptor address Cu...

Page 810: ... data can be located in many buffers When the DMA controller reads a descriptor which the FSG bit in TDES0 is set it knows the current buffer is pointing to a new frame and the first byte of the frame is included When the DMA controller reads a descriptor with FSG bit and LSG bit in TDES0 are both reset it knows the current buffer is pointing to a part of current frame When the DMA controller read...

Page 811: ...error occurs and stops operating at once with error flags written to the DMA status register ENET_DMA_STAT After such fatal error response error occurs application must reset the Ethernet module and reinitialize the DMA controller DMA controller initialization for transmission and reception Before using the DMA controller the initialization must be done as follow steps 1 Set the bus access paramet...

Page 812: ... in TDES0 31 that TxDMA controller read is cleared or any error condition occurs the controller will enter suspend state and at the same time both the transmit buffer unavailable bit in ENET_DMA_STAT and normal interrupt summary bit in ENET_DMA_STAT register are set If entered into suspend state operation proceeds to Step 8 4 When the DAV bit in TDES0 31 of the acquired descriptor is set the DMA d...

Page 813: ... the EOF is transferred If a frame is described with more than one descriptor the intermediate descriptors are all closed by TxDMA controller after fetched 5 The TxDMA controller enters the state of waiting for the transmission status and time stamp of the previous frame if timestamp enabled With writing back status to descriptor the DAV bit is also cleared by TxDMA controller 6 After the whole fr...

Page 814: ... frame on interface is depended on TxDMA mode Cut Through mode or Store and Forward mode The former mode starts sending when the byte number of FIFO is greater than configured threshold and the latter mode starts sending when the whole frame data are transferred into FIFO or when the FIFO is almost full Suspend during transmit polling The DMA controller keeps querying the transmit descriptor after...

Page 815: ... frame have been set 0 The descriptor is available for CPU not for DMA 1 The descriptor is available for DMA not for CPU 30 INTC Interrupt on completion bit This is valid only when the last segment TDES0 29 is set 0 TS bit in ENET_DMA_STAT is not set when frame transmission complete 1 TS bit in ENET_DMA_STAT is set when frame transmission complete 29 LSG Last segment bit This bit indicates that th...

Page 816: ... IP header checksum calculation and insertion 0x2 Enable IP header checksum and payload checksum calculation and insertion pseudo header checksum is not calculated in hardware 0x3 Enable IP Header checksum and payload checksum calculation and insertion pseudo header checksum is calculated in hardware 21 TERM Transmit end for ring mode bit This bit is used only in ring mode and has higher priority ...

Page 817: ...load error TDES0 11 Loss of carrier TDES0 10 No carrier TDES0 9 Late collision TDES0 8 Excessive collision TDES0 2 Excessive deferral TDES0 1 Underflow error 14 JT Jabber timeout bit Only set when the JBD bit is reset 0 No jabber timeout occurred 1 The MAC transmitter has experienced a jabber timeout 13 FRMF Frame flushed bit This bit is set to flush the Tx frame by software 12 IPPE IP payload err...

Page 818: ...mal frame 1 The transmitted frame was a VLAN type frame 6 3 COCNT 3 0 Collision count bits This 4 bit counter value indicates the number of collisions occurring before the frame was transmitted The count is not valid when the ECO bit TDES0 8 is set 2 EXD Excessive deferral bit This is valid when the DFC bit in the MAC configuration register is set 0 No excessive deferral occurred 1 The transmissio...

Page 819: ...es buffer 2 for TCHM 0 or the next descriptor for TCHM 1 TDES2 Transmit descriptor word 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TB1AP TTSL 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TB1AP TTSL 15 0 rw Bits Fields Descriptions 31 0 TB1AP TTSL 31 0 Transmit buffer 1 address pointer Transmit frame timestamp low 32 bit value bits Before transmitting frame application must configure these...

Page 820: ...ler entering running state In running state the RxDMA controller continually fetching the receive descriptors from descriptor table whose starting address is configured in ENET_DMA_RDTADDR register by application If the DAV bit of the fetched receive descriptor is set then this descriptor is used for receiving frame But if the DAV bit is reset which means this receive descriptor cannot be used by ...

Page 821: ... suspend mode the RxDMA controller fetches the next descriptor and the following operation goes to Step 2 Receive descriptor fetching regulation Descriptor fetching occurs if any one or more of the following conditions are met The time SRE bit is configured from 0 to 1 which makes the RxDMA controller entering running state The total buffer size buffer 1 for chain mode or buffer 1 plus buffer 2 fo...

Page 822: ...d a new frame If the DAV bit of the next descriptor is reset the RxDMA controller enters suspend state and sets RBU bit in ENET_DMA_STAT register The pointer value of descriptor address table is retained and be used for the starting descriptor address after exiting suspend state Processing after a new frame received in suspend state When a new frame is available see available definition in the pre...

Page 823: ...d the destination address filter 29 16 FRML 13 0 Frame length bits These bits indicate the byte length of the received frame that was transferred to the buffer including CRC This field is valid only when LDES 1 RDES0 8 and DERR 0 RDES0 14 If LDES 0 and ERRS 0 these bits indicate the accumulated number of bytes that have been transferred for the current frame 15 ERRS Error summary bit This field is...

Page 824: ... partly forwarded to descriptor buffer the overflow error bit sets 0 No overflow error occurred 1 RxFIFO overflowed and frame data is not valid 10 VTAG VLAN tag bit 0 Received frame is not a tag frame 1 Received frame is a tag frame 9 FDES First descriptor bit This bit indicates that current descriptor contains the SOF of the received frame 0 The current descriptor does not store the SOF of the re...

Page 825: ...s active during frame receiving process 0 No receive error occurred 1 Receive error occurred 2 DBERR Dribble bit error bit This bit is valid only in MII interface mode and indicates there is an incomplete byte odd cycles during reception received 0 No dribble bit error occurred 1 Dribble bit error occurred 1 CERR CRC error bit This bit is valid only when the LDES RDES0 8 is set and indicates FCS f...

Page 826: ...sum error detected This error may cased by following condition 1 Type value inconsistent with version value 2 Calculated header checksum mismatch the header checksum field 3 Expected IP header bytes is not received enough 1 1 1 IPv4 or IPv6 frame both header and payload checksum detected errors RDES1 Receive descriptor word 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DINTC Reserved RB2S 12 0...

Page 827: ...ller ignores this buffer and uses buffer 2 RCHM 0 or the next descriptor RCHM 1 RDES2 Receive descriptor word 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RB1AP RTSL 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RB1AP RTSL 15 0 rw Bits Fields Descriptions 31 0 RB1AP RTSL 31 0 Receive buffer 1 address pointer Receive frame timestamp low 32 bit These bits are designed for two different functio...

Page 828: ...ese bits RTSH When timestamp function is enabled and LDES is set these bits will be changed to timestamp high 32 bit value by RxDMA controller if received frame passed the filter and satisfied the snapshoot condition If the received frame does not meet the snapshoot condition these bits will keep RB2AP value 27 3 7 Example for a typical configuration flow of Ethernet After power on reset or system...

Page 829: ...ame data into buffer address which is decided in TDES 2 Set the DAV bit in these one or more transmit frame descriptor 3 Write any value in ENET_DMA_TPEN register to make TxDMA exit suspend state and start transmitting 4 There are two methods for application to confirm whether current transmitting frame is complete or not The first method is that application can poll the DAV bit of current transmi...

Page 830: ...se registers by reading them will need a long time delay depends on the frequency disparity between HCLK and RX_CLK To avoid entering the same event interrupt twice it s strongly recommended that application polls the WUFR and MPKR bit until they reset to zero during the interrupt service routine MAC interrupts All of the MAC events can be read from ENET_MAC_INTF and each of them has a mask bit fo...

Page 831: ...UMI TMSTI Ethernet Interrupt AI AISE FBE FBEIE TPS TPSIE RO ROIE TJT TJTIE RBU RBUIE AND AND AND AND AND OR OR OR TU TUIE RWT RWTIE RPS RPSIE ET ETIE AND AND AND AND AND RS ER TS NI NISE TBU TBUIE AND RIE AND ERIE AND TIE AND OR AND OR Normal Interrupt Abnormal Interrupt ...

Page 832: ...rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 WDD Watchdog disable bit This bit indicates the maximum bytes for receiving data beyond this will be cut off 0 The MAC allows no more than 2048 bytes of the frame being received 1 The MAC disables the watchdog timer on the receiver and can receive frames of up to 16384 bytes 22 JBD Jabber disable bit This bit indicates th...

Page 833: ...plex mode 12 LBM Loopback mode bit 0 The MAC operates in normal mode 1 The MAC operates in loopback mode at the MII 11 DPM Duplex mode bit 0 Half duplex mode enable 1 Full duplex mode enable 10 IPFCO IP frame checksum offload bit 0 The checksum offload function in the receiver is disabled 1 IP frame checksum offload function enabled for received IP frame 9 RTD Retry disable bit This bit is applica...

Page 834: ...ter enable bit 0 The MAC transmit function is disabled after finish the transmission of the current frame and no frames to be transmitted anymore 1 The transmit function of the MAC is enabled for transmission 2 REN Receiver enable bit 0 The MAC reception function is disabled after finish the reception of the current frame and no frames will be received anymore 1 The MAC reception function is enabl...

Page 835: ...address filtering 1 Inverse source address filtering result When SA matches the enabled SA registers filter marks it as failing the SA address filter 7 6 PCFRM 1 0 Pass control frames bits These bits set the forwarding conditions for all control frames including unicast and multicast pause frame For pause control frame the processing not forwarding depends only on RFCEN in ENET_MAC_FCTL 2 0x0 MAC ...

Page 836: ...he filer and DA SA filtering result status in descriptor is always 0 0 Promiscuous mode disabled 1 Promiscuous mode enabled 27 4 3 MAC hash list high register ENET_MAC_HLH Address offset 0x0008 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HLH 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HLH 15 0 rw Bits Fields Descriptions 31 0 HLH 31 0 Hash list high bits These bits t...

Page 837: ...e register address in selected PHY device 5 Reserved Must be kept at reset value 4 2 CLR 2 0 Clock range bits MDC clock divided factor select which is decided by HCLK frequency range 0x0 HCLK 42 HCLK range 60 100 MHz 0x1 HCLK 62 HCLK range 100 120 MHz 0x2 HCLK 16 HCLK range 20 35 MHz 0x3 HCLK 26 HCLK range 35 60 MHz other Reserved 1 PW PHY write bit This bit indicate the PHY operation mode 0 Sendi...

Page 838: ...x0018 Reset value 0x0000 0000 This register configures the generation and reception of the control frames 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PTM 15 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DZQP Reserved PLTS 1 0 UPFDT RFCEN TFCEN FLCB BK PA rw rw rw rw rw rw Bits Fields Descriptions 31 16 PTM 15 0 Pause time bits These bits configured the pause time filed value in transmit ...

Page 839: ...oding function for the received pause frame and process it The MAC disables its transmitter for a specified pause time field value in received frame time 1 TFCEN Transmit flow control enable bit 0 Disable the flow control operation in the MAC Both pause frame sending in Full duplex mode and back pressure feature in Half duplex mode are not performed 1 Enable the flow control operation in the MAC B...

Page 840: ...ctive 0x0 256 bytes 0x1 512 bytes 0x2 768 bytes 0x3 1024 bytes 0x4 1280 bytes 0x5 1536 bytes 0x6 0x7 1792 bytes 3 Reserved Must be kept at reset value 2 0 RFA 2 0 Threshold of active flow control This field configures the threshold of the active flow control If flow control function is enabled when the value of the unprocessed data in RxFIFO is more than this value configured the flow control func...

Page 841: ... 15 13 UP user priority VLTI 12 CFI canonical format indicator VLTI 11 0 VID VLAN identifier When comparison bits VLTI 11 0 if VLTC 1 or VLTI 15 0 if VLTC 0 are all zeros VLAN tag comparison is bypassed and every frame with type filed value of 0x8100 is considered a VLAN frame When comparison bits not all zeros VLAN tag comparison use bit VLTI 11 0 if VLTC 1 or VLTI 15 0 if VLTC 0 for checking 27 ...

Page 842: ...ept at reset value 9 GU Global unicast bit 0 Not all of received unicast frame is considered to be a wakeup frame 1 Any received unicast frame passed address filtering is considered to be a wakeup frame 8 7 Reserved Must be kept at reset value 6 WUFR Wakeup frame received bit This bit is cleared when this register is read 0 Has not received the wake up frame Byte Mask of Filter 0 Byte Mask of Filt...

Page 843: ... hardware When this bit is set MAC drops all received frames When power down mode exit because of wakeup event occurred hardware resets this bit 27 4 12 MAC interrupt flag register ENET_MAC_INTF Address offset 0x0038 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TMST Reserved MSCT MSCR MSC WUM Reserved rc_r r r r r B...

Page 844: ...alue 27 4 13 MAC interrupt mask register ENET_MAC_INTMSK Address offset 0x003C Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TMSTIM Reserved WUMIM Reserved rw rw Bits Fields Descriptions 31 10 Reserved Must be kept at reset value 9 TMSTIM Timestamp trigger interrupt mask bit 0 Unmask the timestamp interrupt generatio...

Page 845: ...uring transmit flow control 27 4 15 MAC address 0 low register ENET_MAC_ADDR0L Address offset 0x0044 Reset value 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR0L 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR0L 15 0 rw Bits Fields Descriptions 31 0 ADDR0L 31 0 MAC addresss0 low 32 bit These bits contain the low 32 bit bit 31 to 0 of the 6 byte MAC address0 These bits are use...

Page 846: ...pare the corresponding byte of received DA SA with the contents of the MAC address1 registers Each bit controls one byte mask as follows MB 5 ENET_MAC_ADDR1H 15 8 MB 4 ENET_MAC_ADDR1H 7 0 MB 3 ENET_MAC_ADDR1L 31 24 MB 2 ENET_MAC_ADDR1L 23 16 MB 1 ENET_MAC_ADDR1L 15 8 MB 0 ENET_MAC_ADDR1L 7 0 23 16 Reserved Must be kept at reset value 15 0 ADDR1H 15 0 MAC address1 high 47 32 bits This field contain...

Page 847: ...sed to comparing with the DA fields of the received frame 1 The MAC address2 47 0 is used to comparing with the SA fields of the received frame 29 24 MB 5 0 Mask byte bits When they are set high the MAC does not compare the corresponding byte of received DA SA with the contents of the MAC address2 registers Each bit controls one byte mask as follows MB 5 ENET_MAC_ADDR2H 15 8 MB 4 ENET_MAC_ADDR2H 7...

Page 848: ... Descriptions 31 AFE Address filter enable bit 0 The address filter ignores the MAC address3 for filtering 1 The address filter use the MAC address3 for perfect filtering 30 SAF Source address filter bit 0 The MAC address3 47 0 is used to comparing with the DA fields of the received frame 1 The MAC address3 47 0 is used to comparing with the SA fields of the received frame 29 24 MB 5 0 Mask byte b...

Page 849: ...scriptions 31 0 ADDR3L 31 0 MAC address3 low 32 bit This field contains the low 32 bit of the 6 byte MAC address3 27 4 22 MSC control register ENET_MSC_CTL Address offset 0x0100 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MCFZ RTOR CTSR CTR rw rw rw rw Bits Fields Descriptions 31 4 Reserved Must be kept at reset va...

Page 850: ...E Reserved rc_r rc_r Bits Fields Descriptions 31 18 Reserved Must be kept at reset value 17 RGUF Received good unicast frames bit 0 Good unicast frame received counter is less than half of the maximum value 1 Good unicast frame received counter reaches half of the maximum value 16 7 Reserved Must be kept at reset value 6 RFAE Received frames alignment error bit 0 Alignment error frame received cou...

Page 851: ...Good frame after more than a single collision transmitted counter reaches half of the maximum value 14 TGFSC Transmitted good frames single collision bit 0 Good frame after a single collision transmitted counter is less than half of the maximum value 1 Good frame after a single collision transmitted counter reaches half of the maximum value 13 0 Reserved Must be kept at reset value 27 4 25 MSC rec...

Page 852: ...fset 0x0110 Reset value 0x0000 0000 The MSC transmit interrupt mask register configures the mask bits for interrupts generation 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TGFIM Reserved rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TGFMSCIM TGFSCIM Reserved rw rw Bits Fields Descriptions 31 22 Reserved Must be kept at reset value 21 TGFIM Transmitted good frames interrupt mask bit 0 Unmas...

Page 853: ...gle collision counter bits These bits count the number of a transmitted good frames after only a single collision 27 4 28 MSC transmitted good frames after more than a single collision counter register ENET_MSC_MSCCNT Address offset 0x0150 Reset value 0x0000 0000 This register counts the number of successfully transmitted frames after more than one single collision in Half duplex mode 31 30 29 28 ...

Page 854: ... 30 MSC received frames with CRC error counter register ENET_MSC_RFCECNT Address offset 0x0194 Reset value 0x0000 0000 This register counts the number of frames received with CRC error 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RFCER 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFCER 15 0 r Bits Fields Descriptions 31 0 RFCER 31 0 Received frames with CRC error counter bits These bits count ...

Page 855: ...nts the number of good unicast frames received 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RGUF 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGUF 15 0 r Bits Fields Descriptions 31 0 RGUF 31 0 Received good unicast frames counter bits These bits count the number of good unicast frames received 27 4 33 PTP time stamp control register ENET_PTP_TSCTL Address offset 0x0700 Reset value 0x0000 0000...

Page 856: ...racted from with the value specified in the timestamp update high and low registers It is cleared by hardware when the update finished 2 TMSSTI Timestamp system time initialize bit This bit must be read as zero before application set it 0 The system time is maintained without any change 1 Initializing the system time with the value in timestamp update high and low registers It is cleared by hardwa...

Page 857: ...p high register ENET_PTP_TSH Address offset 0x0708 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STMS 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STMS 15 0 r Bits Fields Descriptions 31 0 STMS 31 0 System time second bits These bits show the current second of the system time 27 4 36 PTP time stamp low register ENET_PTP_TSL Address offset 0x070C Reset value 0x0000 0000 3...

Page 858: ...C core Application must write both of these registers before setting the TMSSTI or TMSSTU bits in the timestamp control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TMSUS 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMSUS 15 0 rw Bits Fields Descriptions 31 0 TMSUS 31 0 Time stamp update second bits These bits are used for initializing or adding subtracting to second of the system ti...

Page 859: ...tor in every clock cycle and the system time updates when the accumulator reaches overflow 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TMSA 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMSA 15 0 rw Bits Fields Descriptions 31 0 TMSA 31 0 Time stamp addend bits These registers contain a 32 bit time value which is added to the accumulator register to achieve time synchronization 27 4 40 PTP ex...

Page 860: ...ed DPSL 4 0 DAB SWR rw rw rw rw rs Bits Fields Descriptions 31 26 Reserved Must be kept at reset value 25 AA Address aligned bit 0 Disable address aligned 1 Enabled address aligned If the FB 1 all AHB interface address is aligned to the start address LS bits bit 1 to 0 If the FB 0 the AHB interface first access address accessing the data buffer s start address is not aligned but subsequent burst a...

Page 861: ...io bits These bits indicate the access ratio between RxDMA and TxDMA 0x0 RxDMA TxDMA 1 1 0x1 RxDMA TxDMA 2 1 0x2 RxDMA TxDMA 3 1 0x3 RxDMA TxDMA 4 1 Note This bit is valid only when the arbitration mode is Round robin DAB 0 13 8 PGBL 5 0 Programmable burst length bits These bits indicate the maximum number of beats to be transferred in one DMA transaction When UIP 1 the PGBL value is only used for...

Page 862: ...MA controller poll the transmit descriptor table The TxDMA controller can go into suspend state because of an underflow error in a transmitted frame or the descriptor unavailable DAV 0 Application can write any value into this register for attempting to re fetch the current descriptor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TPE 31 16 rw_wt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPE 15 0 rw_...

Page 863: ...ss register ENET_DMA_RDTADDR Address offset 0x100C Reset value 0x0000 0000 This register points to the start of the receive descriptor table The descriptor table is located in the physical memory space and must be word aligned This register can only be written when RxDMA controller is in stop state Before starting RxDMA reception process this register must be configured correctly 31 30 29 28 27 26...

Page 864: ...them but writing 0 has no effect Each bit bits 16 0 can be masked by masking the corresponding bit in the ENET_DMA_INTEN register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TST WUM MSC Reserved EB 2 0 TP 2 0 RP 2 0 NI r r r r r r rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AI ER FBE Reserved ET RWT RPS RBU RS TU RO TJT TBU TPS TS rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 ...

Page 865: ...t These bits decode the TxDMA state 0x0 Stopped Reset or Stop Transmit Command issued 0x1 Running Fetching transmit transfer descriptor 0x2 Running Waiting for status 0x3 Running Reading Data from host memory buffer and queuing it to transmit buffer TxFIFO 0x4 0x5 Reserved 0x6 Suspended Transmit descriptor unavailable or transmit buffer underflow 0x7 Running Closing transmit descriptor 19 17 RP 2 ...

Page 866: ...n this bit is set application must cleared its source bit by writing 1 to that bit 14 ER Early receive status bit This bit is automatically cleared when the ENET_DMA_STAT 6 is set 0 The first buffer has not been filled 1 The first buffer has filled with received frame 13 FBE Fatal bus error status bit This bit indicates a response error on AHB interface is occurred and the error type can be decode...

Page 867: ...ransmission 1 The transmit jabber timer expired The TxDMA controller cancels the current transmission and enters stop state This also causes JT bit in TDES0 set 2 TBU Transmit buffer unavailable status bit 0 The DAV bit in fetched next transmit descriptor is set 1 The DAV bit in fetched next transmit descriptor is reset and TxDMA enters suspend state 1 TPS Transmit process stopped status bit 0 The...

Page 868: ... RxDMA does not flush any frames even though receive descriptor is unavailable 23 22 Reserved Must be kept at reset value 21 TSFD Transmit Store and Forward bit 0 The TxFIFO operates in Cut Through mode The TTHC bits in ENET_DMA_CTL register defines the start popping time from TxFIFO 1 The TxFIFO operates in Store and Forward mode Transmission on interface starts after the full frame has been push...

Page 869: ...be kept at reset value 7 FERF Forward error frames bit 0 When RxFIFO is in Cut Through mode RSFD 0 if frame error CRC error collision error checksum error watchdog timeout overflow error is detected before popping RxFIFO data to memory RxFIFO drops this error frame But if frame error is detected after popping RxFIFO data to memory RxFIFO will not drop this frame data When RxFIFO is in Store and Fo...

Page 870: ...an either from current address in the ENET_DMA_RDTADDR register or the address after previous frame stopped by application If the DAV bit in fetched descriptor is reset RxDMA controller will enter suspend state and RBU bit will be set This bit can be set only when RxDMA controller is in stop state or suspend state This bit should be set after all other DMA registers have been configured otherwise ...

Page 871: ... 1 The early receive interrupt is enabled 13 FBEIE Fatal bus error interrupt enable bit 0 The fatal bus error enable interrupt is disabled 1 The fatal bus error enable interrupt is enabled 12 11 Reserved Must be kept at reset value 10 ETIE Early transmit interrupt enable bit 0 The early transmit interrupt is disabled 1 The early transmit interrupt is enabled 9 RWTIE Receive watchdog timeout interr...

Page 872: ...upt is disabled 1 The transmission stopped interrupt is enabled 0 TIE Transmit interrupt enable bit 0 The transmit interrupt is disabled 1 The transmit interrupt is enabled 27 4 50 DMA missed frame and buffer overflow counter register ENET_DMA_MFBOCNT Address offset 0x1020 Reset value 0x0000 0000 There are two counters designed in DMA controller for tracking the number of missed frames during rece...

Page 873: ...to the start descriptor address of the current transmit descriptor read by the TxDMA controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TDAP 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TDAP 15 0 r Bits Fields Descriptions 31 0 TDAP 31 0 Transmit descriptor address pointer bits These bits are automatically updated by TxDMA controller during operation 27 4 52 DMA current receive descriptor...

Page 874: ...12 11 10 9 8 7 6 5 4 3 2 1 0 TBAP 15 0 r Bits Fields Descriptions 31 0 TBAP 31 0 Transmit buffer address pointer bits These bits are automatically updated by TxDMA controller during operation 27 4 54 DMA current receive buffer address register ENET_DMA_CRBADDR Address offset 0x1054 Reset value 0x0000 0000 This register points to the current receive buffer address being read by the RxDMA controller...

Page 875: ... Supports OTG protocol with HNP Host Negotiation Protocol and SRP Session Request Protocol Supports all the 4 types of transfer control bulk interrupt and isochronous Includes a USB transaction scheduler in host mode to handle USB transaction request efficiently Includes a 1 25KB FIFO RAM Supports 8 channels in host mode Includes 2 Tx FIFOs periodic and non periodic and 1 Rx FIFO shared by all cha...

Page 876: ...fication Mini connector identification port 28 5 Function overview 28 5 1 USBFS clocks and working modes USBFS could be operated as a host a device or a DRD Dual role Device it contains an internal full speed PHY The maximum speed supported by USBFS is full speed The internal PHY supports Full Speed and Low Speed in host mode supports full speed in device mode and supports OTG mode with HNP and SR...

Page 877: ...S works in device mode FHM bit is cleared and FDM bit is set the VBUS detection circuit is configured by VBUSIG bit in USBFS_GCCFG register So if the device does not need to detect the voltage on VBUS pin it could be configured by setting the VBUSIG bit then the VBUS pin can be freed for other uses Otherwise the VBUS connection cannot be omitted and USBFS continuously monitors the VBUS voltage It ...

Page 878: ...ed on and the USB port changes into disconnected state After a connection is detected USB port changes into connected state The USB port changes into enabled state after a port reset is performed on USB bus Figure 28 4 State transition diagram of host port Power off Dis connected Connected Enabled set PP bit clear PP bit or VBUS is not valid in OTG host mode connection event disconnection event po...

Page 879: ...ed in USB 2 0 protocol SOF packets are generated by the host controller or hub transaction translator every 1ms in full speed links Once that USBFS entered into enabled state it will send the SOF packet periodically and the period is defined in USB 2 0 protocol In addition application may adjust the length of a frame by writing FRI field in USBFS_HFT registers The FRI bits define the number of USB...

Page 880: ...l employ SIE to generate this transaction on USB bus When the required bus time for the current request is not enough in the current frame and this is a periodic request USBFS stops processing the periodic queue and starts to process non periodic request If this is a non periodic queue the USBFS will stop processing any queue and wait until the end of current frame 28 5 3 USB device function USB D...

Page 881: ...SB bus time reaches EOF1 or EOF2 point End of Frame described in USB 2 0 protocol USBFS will trigger an EOPFIF interrupt in USBFS_GINTF register These flags and registers can be used to get current bus time and position information 28 5 4 OTG function overview USBFS supports OTG function described in OTG protocol 1 3 OTG function includes SRP and HNP protocols A Device and B Device A Device is an ...

Page 882: ...is no bus activity while still providing a means for the B Device to initiate bus activity As is described in OTG protocol an OTG device must compare VBUS voltage with several threshold values and the compared result should be reported in ASV and BSV bits in USBFS_GOTGCS register Set SRPREQ bit in USBFS_GOTGCS register to start a SRP request when USBFS is in OTG B Device mode USBFS will generate a...

Page 883: ... same FIFO It is important for USBFS to get which channel the current pushed packet belongs to and the Rx FIFO which the packet belongs to is also able to be accessed by using USBFS_GRSTATR USBFS_GRSTATP register Figure 28 6 Host mode FIFO access register mapping CH0 FIFO Write Read CH1 FIFO Write Read 1000h 1FFFh CH7 FIFO Write Read 2000h 2FFFh 8000h 8FFFh Device mode In device mode the data FIFO...

Page 884: ... 8 Device mode FIFO access register mapping describes the register memory area where the data FIFO can access The addresses in the figure are addressed in bytes Each endpoint has its own FIFO access register space Rx FIFO is also able to be accessed by using USBFS_GRSTATR USBFS_GRSTATP register Figure 28 8 Device mode FIFO access register mappimg IEP0 FIFO Write IEP1 FIFO Write 1000h 1FFFh IEP3 FI...

Page 885: ...y enabled Read PS 1 0 bits to get the connected device s speed and then program USBFS_HFT register to change the SOF interval if needed Channel initialization and enable sequence 1 Program USBFS_HCHxCTL registers with desired transfer type direction packet size etc Ensure that CEN and CDIS bits are kept cleared during configuration 2 Program USBFS_HCHxINTEN register Set the desired interrupt enabl...

Page 886: ...handshake received USBFS pushes the received data packet into the Rx FIFO and triggers ACK flag Otherwise the status flag NAK reports the transaction result 7 If the IN transaction described in step 5 is successful and PCNT is larger than 1 in step2 returns to step 3 and continues to receive the remaining packets If the IN transaction described in step 5 is not successful returns to step 3 to re r...

Page 887: ...Program USBFS_GAHBCS register according to application s demand such as the TxFIFO s empty threshold etc GINTEN bit should be kept cleared at this time 2 Program USBFS_GUSBCS register according to application s demand such as the operation mode host device or OTG and some parameters of OTG and USB protocols 3 Program USBFS_GCCFG register according to application s demand 4 Program USBFS_GRFLEN USB...

Page 888: ...egisters 2 Initialize and enable the IN endpoint 3 Write packets into the endpoint s Tx FIFO At any time a data packet is written into the FIFO USBFS decreases the TLEN field in USBFS_DIEPxLEN register by the written packet s size 4 When an IN token received USBFS transmits the data packet and after the transaction finishes on USB bus PCNT in USBFS_DIEPxLEN register is decreased by 1 If the transa...

Page 889: ...USBFS global interrupt Interrupt Flag Description Operation Mode SEIF Session interrupt Host or device mode DISCIF Disconnect interrupt flag Host Mode IDPSC ID pin status change Host or device mode PTXFEIF Periodic Tx FIFO empty interrupt flag Host Mode HCIF Host channels interrupt flag Host Mode HPIF Host port interrupt flag Host Mode ISOONCIF PXN CIF Isochronous OUT transfer not complete interru...

Page 890: ...c Tx FIFO empty interrupt flag Host Mode RXFNEIF Rx FIFO non empty interrupt flag Host or device mode SOF Start of frame Host or device mode OTGIF OTG interrupt flag Host or device mode MFIF Mode fault interrupt flag Host or device mode Wakeup interrupt can be triggered when USBFS is in suspend state even if when the USBFS s clocks are stopped The source of the wakeup interrupt is WKUPIF bit in US...

Page 891: ...lue 19 BSV B Session Valid described in OTG protocol 0 Vbus voltage level of a OTG B Device is below VBSESSVLD 1 Vbus voltage level of a OTG B Device is not below VBSESSVLD Note Only accessible in OTG B Device mode 18 ASV A Session valid A host mode transceiver status 0 Vbus voltage level of a OTG A Device is below VASESSVLD 1 Vbus voltage level of a OTG A Device is below VASESSVLD The A Device is...

Page 892: ...not enabled 1 HNP function is enabled Note Only accessible in host mode 9 HNPREQ HNP request This bit is set by software to start a HNP on the USB When HNPEND bit in USBFS_GOTGINTF register is set this bit can be cleared by writing zero to it or clearing the HNPEND bit in USBFS_GOTGINTF register 0 Don t send HNP request 1 Send HNP request Note Only accessible in device mode 8 HNPS HNP successes Th...

Page 893: ... HNPEND SRPEND Reserved SESEND Reserved rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 DF Debounce finish Set by USBFS when the debounce is done during device connection Note Only accessible in host mode 18 ADTO A Device timeout Set by USBFS when it is timed out for the A Device waiting for a B Device connection Note Accessible in both device and host mode...

Page 894: ...ccessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PTXFTH TXFTH Reserved GINTEN rw rw rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 PTXFTH Periodic Tx FIFO threshold 0 PTXFEIF will be triggered when the periodic Tx FIFO is half empty 1 PTXFEIF will be triggered when the periodic Tx FIFO is complet...

Page 895: ... FHM Reserved rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UTT 3 0 HNPCEN SRPCEN FSSTS TOC 2 0 rw r rw r rw r rw Bits Fields Descriptions 31 Reserved Must be kept at reset value 30 FDM Force device mode Setting this bit will force the core to device mode irrespective of the USBFS ID input pin 0 Normal mode 1 Device mode The application must wait at least 25 ms for the change taking effect ...

Page 896: ...e Accessible in both device and host modes 7 FSSTS Full speed serial transceiver select always 1 with read only 6 3 Reserved Must be kept at reset value 2 0 TOC 2 0 Timeout calibration USBFS always uses time out value required in USB 2 0 when waiting for a packet The TOC bits are used to add the value in terms of PHY clock The frequency of PHY clock is 48MHz Global reset control register USBFS_GRS...

Page 897: ...should wait until this bit is cleared before any other operation on USBFS Note Accessible in both device and host modes 4 RXFF Rx FIFO flush Set the bit to flush data Rx FIFO Hardware automatically clears this bit after the flush process completes After setting this bit application should wait until this bit is cleared before any other operation on USBFS Note Accessible in both device and host mod...

Page 898: ...c_w1 rc_w1 rc_w1 r r r r rc_w1 r rc_w1 r Bits Fields Descriptions 31 WKUPIF Wakeup interrupt flag This interrupt is triggered when a resume signal in device mode or a remote wakeup signal in host mode is detected on the USB Note Accessible in both device and host modes 30 SESIF Session interrupt flag This interrupt is triggered when a SRP is detected in A Device mode or VBUS becomes valid for a B ...

Page 899: ...ot completed at the end of current frame Host mode Isochronous OUT transfer Not Complete Interrupt Flag At the end of a periodic frame defined by EOPFT bit in USBFS_DCFG USBFS will set this bit if there are still isochronous OUT endpoints for the transactions not completed Device Mode 20 ISOINCIF Isochronous IN transfer Not Complete Interrupt Flag At the end of a periodic frame defined by EOPFT bi...

Page 900: ...ce mode 12 RST USB reset USBFS sets this bit when it detects a USB reset signal on bus Note Only accessible in device mode 11 SP USB suspend USBFS sets this bit when it detects that the USB bus is idle for 3 ms and enters suspend state Note Only accessible in device mode 10 ESP Early suspend USBFS sets this bit when it detects that the USB bus is idle for 3 ms Note Only accessible in device mode 9...

Page 901: ...urce of this interrupt This bit is cleared after the flags in USBFS_GOTGINTF causing this interrupt are cleared Note Accessible in both host and device modes 1 MFIF Mode fault interrupt flag USBFS sets this bit when software operates host only register in device mode or operates device only register in host mode These fault operations won t take effect Note Accessible in both host and device modes...

Page 902: ...ote Accessible in both host and device modes 29 DISCIE Disconnect interrupt enable 0 Disable disconnect interrupt 1 Enable disconnect interrupt Note Only accessible in device mode 28 IDPSCIE ID pin status change interrupt enable 0 Disable connector ID pin status interrupt 1 Enable connector ID pin status interrupt Note Accessible in both host and device modes 27 Reserved Must be kept at reset valu...

Page 903: ...EPIE OUT endpoints interrupt enable 0 Disable OUT endpoints interrupt 1 Enable OUT endpoints interrupt Note Only accessible in device mode 18 IEPIE IN endpoints interrupt enable 0 Disable IN endpoints interrupt 1 Enable IN endpoints interrupt Note Only accessible in device mode 17 16 Reserved Must be kept at reset value 15 EOPFIE End of periodic frame interrupt enable 0 Disable end of periodic fra...

Page 904: ...ble global non periodic IN NAK effective interrupt Note Only accessible in device mode 5 NPTXFEIE Non periodic Tx FIFO empty interrupt enable 0 Disable non periodic Tx FIFO empty interrupt 1 Enable non periodic Tx FIFO empty interrupt Note Only accessible in Host mode 4 RXFNEIE Receive FIFO non empty interrupt enable 0 Disable receive FIFO non empty interrupt 1 Enable receive FIFO non empty interr...

Page 905: ... after when Receive FIFO non empty interrupt flag bit of the global interrupt flag register RXFNEIF bit in USBFS_GINTF is triggered This register has to be accessed by word 32 bit Host mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RPCKST 3 0 DPID r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPID BCOUNT 10 0 CNUM 3 0 r r r Bits Fields Descriptions 31 21 Reserved Must be kept at reset v...

Page 906: ...ns 31 21 Reserved Must be kept at reset value 20 17 RPCKST 3 0 Received packet status 0001 Global OUT NAK generates an interrupt 0010 OUT data packet received 0011 OUT transfer completed generates an interrupt 0100 SETUP transaction completed generates an interrupt 0110 SETUP data packet received Others Reserved 16 15 DPID 1 0 Data PID The Data PID of the received OUT data packet 00 DATA0 10 DATA1...

Page 907: ...s Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 RXFD 15 0 Rx FIFO depth In terms of 32 bit words 1 RXFD 1024 Host non periodic Tx FIFO length register Device IN endpoint 0 Tx FIFO length USBFS_HNPTFLEN _DIEP0TFLEN Address offset 0x028 Reset value 0x0200 0200 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HNPTXFD IEP0TXFD 15 0 r...

Page 908: ...s in term of 32 bit words Host non periodic Tx FIFO queue status register USBFS_HNPTFQSTAT Address offset 0x002C Reset value 0x0008 0200 This register reports the current status of the non periodic Tx FIFO and request queue The request queue holds IN OUT or other request entries in host mode Note In Device mode this register is not valid This register has to be accessed by word 32 bit 31 30 29 28 ...

Page 909: ...ntries n n entries 0 n 8 Others Reserved 15 0 NPTXFS 15 0 Non periodic Tx FIFO space The remaining space of the non periodic Tx FIFO In terms of 32 bit words 0 Non periodic Tx FIFO is full 1 1 word 2 2 words n n words 0 n NPTXFD Others Reserved Global core configuration register USBFS_GCCFG Address offset 0x0038 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27...

Page 910: ...e comparer enable 0 VBUS B device comparer disabled 1 VBUS B device comparer enabled 18 VBUSACEN The VBUS A device comparer enable 0 VBUS A device comparer disabled 1 VBUS A device comparer enabled 17 Reserved Must be kept at reset value 16 PWRON Power on This bit is the power switch for the internal embedded full speed PHY 0 Embedded full speed PHY power off 1 Embedded full speed PHY power on 15 ...

Page 911: ... 23 22 21 20 19 18 17 16 HPTXFD 15 0 r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HPTXFSAR 15 0 r rw Bits Fields Descriptions 31 16 HPTXFD 15 0 Host periodic Tx FIFO depth In terms of 32 bit words 1 HPTXFD 1024 15 0 HPTXFSAR 15 0 Host periodic Tx FIFO RAM start address The start address for host periodic Tx FIFO RAM is in term of 32 bit words Device IN endpoint Tx FIFO length register USBFS_DIEPxTFL...

Page 912: ... FIFO RAM start address The start address for IN endpoint Tx FIFO is in term of 32 bit words 28 7 2 Host control and status registers Host control register USBFS_HCTL Address offset 0x0400 Reset value 0x0000 0000 This register configures the core after power on in host mode It is not need to modify it after host initialization This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24...

Page 913: ... 11 10 9 8 7 6 5 4 3 2 1 0 FRI 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 FRI 15 0 Frame interval This value describes the frame time in terms of PHY clocks Each time when port is enabled after a port reset USBFS uses a proper value according to the current speed and software can write to this field to change the value This value should be calculated using the...

Page 914: ...dic Tx FIFO queue status register USBFS_HPTFQSTAT Address offset 0x0410 Reset value 0x0008 0200 This register reports the current status of the host periodic Tx FIFO and request queue The request queue includes IN OUT or other request entries in host mode This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PTXREQT 7 0 PTXREQS 7 0 r r 15 14 13 12 11 10 9 ...

Page 915: ...odic Tx FIFO space The remaining space of the periodic Tx FIFO In terms of 32 bit words 0 periodic Tx FIFO is full 1 1 word 2 2 words n n words 0 n PTXFD Others Reserved Host all channels interrupt register USBFS_HACHINT Address offset 0x0414 Reset value 0x0000 0000 When a channel interrupt is triggered USBFS sets a corresponding bit in this register and software should read this register to know ...

Page 916: ...to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CINTEN 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 CINTEN 7 0 Channel interrupt enable 0 Disable channel n interrupt 1 Enable channel n interrupt Each bit represents a channel Bit 0 for channel 0 bit 7 for channel 7 Host port contro...

Page 917: ...sn t have power supply ability it only uses this bit to get whether the port is in powered state Software should ensure the power supply on VBUS before setting this bit 0 Port is powered off 1 Port is powered on 11 10 PLST 1 0 Port line status Report the current state of USB data lines Bit 10 State of DP line Bit 11 State of DM line 9 Reserved Must be kept at reset value 8 PRST Port reset Applicat...

Page 918: ... 1 Over current condition 3 PEDC Port enable disable change Set by the core when the status of the Port enable bit 2 in this register changes 2 PE Port Enable This bit is automatically set by USBFS after a USB reset signal finishes and cannot be set by software This bit is cleared by the following events A disconnection condition Software clears this bit 0 Port disabled 1 Port enabled 1 PCD Port c...

Page 919: ...oftware should follow the operation guide to disable or enable a channel 29 ODDFRM Odd frame For periodic transfers interrupt or isochronous transfer this bit controls that channel s transaction to be processed is in odd frame or even frame 0 Even frame 1 Odd frame 28 22 DAR 6 0 Device address The address of the USB device that this channel wants to communicate with 21 20 Reserved Must be kept at ...

Page 920: ... flag bits in this register are all set by hardware and cleared by writing 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DTER REQOVR BBER USBER Reserved ACK NAK STALL Reserved CH TF rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 11 Reserved Must be kept at ...

Page 921: ...ansfer finished All the transactions of this channel finish successfully and no error occurs For IN channel this flag will be triggered after PCNT bits in USBFS_HCHxLEN register reach zero For OUT channel this flag will be triggered when software reads and pops a TF status entry from the Rx FIFO Host channel x interrupt enable register USBFS_HCHxINTEN x 0 7 where x channel number Address offset 0x...

Page 922: ...IE Babble error interrupt enable 0 Disable babble error interrupt 1 Enable babble error interrupt 7 USBERIE USB bus error interrupt enable 0 Disable USB bus error interrupt 1 Enable USB bus error interrupt 6 Reserved Must be kept at reset value 5 ACKIE ACK interrupt enable 0 Disable ACK interrupt 1 Enable ACK interrupt 4 NAKIE NAK interrupt enable 0 Disable NAK interrupt 1 Enable NAK interrupt 3 S...

Page 923: ...A PID of the first transmitted packet For IN transfers this field controls the expected DATA PID of the first received packet and DTERR will be triggered if the DATA PID doesn t match After the transfer starts USBFS changes and toggles this field automatically following the USB protocol 00 DATA0 10 DATA1 11 SETUP for control transfer only 01 Reserved 28 19 PCNT 9 0 Packet count The number of data ...

Page 924: ...t is not able to change this register after device initialization This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EOPFT 1 0 DAR 6 0 Res NZLSOH DS 1 0 rw rw rw rw Bits Fields Descriptions 31 13 Reserved Must be kept at reset value 12 11 EOPFT 1 0 End of periodic frame time This field defines the ...

Page 925: ...thers Reserved Device control register USBFS_DCTL Address offset 0x0804 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved POIF CGONAK SGONAK CGINAK SGINAK Reserved GONS GINS SD RWKUP rw w w w w r r rw rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11...

Page 926: ...oesn t save the incoming OUT data packet 2 GINS Global IN NAK status 0 The response to IN transaction is decided by Tx FIFO status endpoint s NAK and STALL bits 1 USBFS always responses to IN transaction with a NAK handshake 1 SD Soft disconnect Software can use this bit to generate a soft disconnection condition on USB bus After this bit is set USBFS switches off the pull up resistor on DP line T...

Page 927: ...ag in USBFS_GINTF register is triggered 11 Full speed Others reserved 0 SPST Suspend status This bit reports whether device is in suspend state 0 Device is in suspend state 1 Device is not in suspend state Device IN endpoint common interrupt enable register USBFS_DIEPINTEN Address offset 0x810 Reset value 0x0000 0000 This register contains the interrupt enable bits for the flags in USBFS_DIEPxINTF...

Page 928: ...isabled interrupt enable bit 0 Disable endpoint disabled interrupt 1 Enable endpoint disabled interrupt 0 TFEN Transfer finished interrupt enable bit 0 Disable transfer finished interrupt 1 Enable transfer finished interrupt Device OUT endpoint common interrupt enable register USBFS_DOEPINTEN Address offset 0x0814 Reset value 0x0000 0000 This register contains the interrupt enable bits for the USB...

Page 929: ... endpoint Rx FIFO overrun interrupt 3 STPFEN SETUP phase finished only for control OUT endpoint interrupt enable bit 0 Disable SETUP phase finished interrupt 1 Enable SETUP phase finished interrupt 2 Reserved Must be kept at reset value 1 EPDISEN Endpoint disabled interrupt enable bit 0 Disable endpoint disabled interrupt 1 Enable endpoint disabled interrupt 0 TFEN Transfer finished interrupt enab...

Page 930: ...IN endpoint interrupt bits Each bit represents an IN endpoint Bit 0 for IN endpoint 0 bit 3 for IN endpoint 3 Device all endpoints interrupt enable register USBFS_DAEPINTEN Address offset 0x081C Reset value 0x0000 0000 This register can be used by software to enable or disable an endpoint s interrupt Only when the endpoint whose corresponding bit in this register is set it is able to trigger the e...

Page 931: ...h bit represents an IN endpoint Bit 0 for IN endpoint 0 bit 3 for IN endpoint 3 Device VBUS discharge time register USBFS_DVBUSDT Address offset 0x0828 Reset value 0x0000 17D7 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DVBUSDT 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset val...

Page 932: ...et value 11 0 DVBUSPT 11 0 Device VBUS pulsing time This field defines the pulsing time for VBUS The true pulsing time is 1024 DVBUSPT 11 0 TUSBCLOCK where TUSBCLOCK is the period time of USB clock Device IN endpoint FIFO empty interrupt enable register USBFS_DIEPFEINTEN Address offset 0x0834 Reset value 0x0000 0000 This register contains the enable bits for the Tx FIFO empty interrupts of IN endp...

Page 933: ...SBFS_DIEP0CTL Address offset 0x0900 Reset value 0x0000 8000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EPEN EPD Reserved SNAK CNAK TXFNUM 3 0 STALL Reserved EPTYPE 1 0 NAKS Reserved rs rs w w rw rs r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EPACT Reserved MPL 1 0 r rw Bits Fields Descriptions 31 EPEN Endpoint enable Set by the application and cle...

Page 934: ...e kept at reset value 19 18 EPTYPE 1 0 Endpoint type This field is fixed to 00 for control endpoint 17 NAKS NAK status This bit controls the NAK status of USBFS when both STALL bit in this register and GINS bit in USBFS_DCTL register are cleared 0 USBFS sends data or handshake packets according to the status of the endpoint s Tx FIFO 1 USBFS always sends NAK handshake to the IN token This bit is r...

Page 935: ...should follow the operation guide to disable or enable an endpoint 30 EPD Endpoint disable Software can set this bit to disable the endpoint Software should follow the operation guide to disable or enable an endpoint 29 SODDFRM SD1PID Set odd frame For isochronous IN endpoints This bit has effect only if this is an isochronous IN endpoint Software sets this bit to set EOFRM bit in this register Se...

Page 936: ...e NAK status of USBFS when both STALL bit in this register and GINS bit in USBFS_DCTL register are are cleared 0 USBFS sends data or handshake packets according to the status of the endpoint s Tx FIFO 1 USBFS always sends NAK handshake to the IN token This bit is read only and software should use CNAK and SNAK in this register to control this bit 16 EOFRM DPID Even odd frame For isochronous IN end...

Page 937: ...PEN EPD Reserved SNAK CNAK Reserved STALL SNOOP EPTYPE 1 0 NAKS Reserved rs r w w rs rw r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EPACT Reserved MPL 1 0 r r Bits Fields Descriptions 31 EPEN Endpoint enable Set by the application and cleared by USBFS 0 Endpoint disabled 1 Endpoint enabled Software should follow the operation guide to disable or enable an endpoint 30 EPD Endpoint disable This bit is...

Page 938: ...er are cleared 0 USBFS sends data or handshake packets according to the status of the endpoint s Rx FIFO 1 USBFS always sends NAK handshake for the OUT token This bit is read only and software should use CNAK and SNAK in this register to control this bit 16 Reserved Must be kept at reset value 15 EPACT Endpoint active This field is fixed to 1 for endpoint 0 14 2 Reserved Must be kept at reset valu...

Page 939: ...bit has effect only if this is an isochronous OUT endpoint Software sets this bit to set EOFRM bit in this register Set DATA1 PID For interrupt bulk OUT endpoints Software sets this bit to set DPID bit in this register 28 SEVENFRM SD0PID Set even frame For isochronous OUT endpoints Software sets this bit to clear EOFRM bit in this register Set DATA0 PID For interrupt bulk OUT endpoints Software se...

Page 940: ... FIFO 1 USBFS always sends NAK handshake to the OUT token This bit is read only and software should use CNAK and SNAK in this register to control this bit 16 EOFRM DPID Even odd frame for isochronous OUT endpoints For isochronous transfers software can use this bit to control that USBFS only receives data packets in even or odd frames If the current frame number s parity doesn t match with this bi...

Page 941: ...ssed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TXFE IEPNE Reserved EPTXFUD CITO Reserved EPDIS TF r rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 TXFE Tx FIFO empty The Tx FIFO of this IN endpoint has reached the empty threshold value defined by TXFTH field in USBFS_GAH...

Page 942: ... this register for the respective endpoint to get the source of the interrupt The flag bits in this register are all set by hardware and cleared by writing 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BTBSTP Reserved EPRXFOVR STPF Reserved EPDIS TF rc_w1 rw rc_w1 rc_w1 rc_w1 rc_w1 Bits Fiel...

Page 943: ...s to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PCNT 1 0 Reserved rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TLEN 6 0 rw Bits Fields Descriptions 31 21 Reserved Must be kept at reset value 20 19 PCNT 1 0 Packet count The number of data packets desired to be transmitted in a transfer Program this field before the endpoint is enabled After the transfer...

Page 944: ...ram this field before setup transfers Each time a back to back setup packet is received USBFS decreases this field by one When this field reaches zero the BTBSTP flag in USBFS_DOEP0INTF register will be triggered 00 0 packet 01 1 packet 10 2 packets 11 3 packets 28 20 Reserved Must be kept at reset value 19 PCNT Packet count The number of data packets desired to receive in a transfer Program this ...

Page 945: ...nt per frame This field indicates the packet count that must be transmitted per frame for periodic IN endpoints on the USB It is used to calculate the data PID for isochronous IN endpoints by the core 01 1 packet 10 2 packets 11 3 packets 28 19 PCNT 9 0 Packet count The number of data packets desired to be transmitted in a transfer Program this field before the endpoint is enabled After the transf...

Page 946: ...atest received data packet on this endpoint 00 DATA0 10 DATA1 Others Reserved SETUP packet count for control OUT Endpoints This field defines the maximum number of back to back SETUP packets this endpoint can accept Program this field before SETUP transfers Each time a back to back SETUP packet is received USBFS decreases this field by one When this field reaches zero the BTBSTP flag in USBFS_DOEP...

Page 947: ...0x0000 0200 This register contains the information of each endpoint s Tx FIFO This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IEPTFS 15 0 r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 IEPTFS 15 0 IN endpoint s Tx FIFO remaining space IN endpoint s Tx FIFO remaining space is i...

Page 948: ... SHCLK SUCLK rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 SHCLK Stop HCLK Stop the HCLK to save power 0 HCLK is not stopped 1 HCLK is stopped 0 SUCLK Stop the USB clock Stop the USB clock to save power 0 USB clock is not stopped 1 USB clock is stopped ...

Page 949: ...ble 29 1 Revision history Revision No Description Date 1 0 Initial Release Jul 1 2015 2 0 Adapt To New Name Convention Jun 5 2017 2 1 Adapt To New Document Specification Oct 25 2018 2 2 Modify the ENET RxDMA descriptor word 0 RDES0 Bit15 Oct 8 2019 ...

Page 950: ...y business industrial personal and or household applications only The Products are not designed intended or authorized for use as components in systems designed or intended for the operation of weapons weapons systems nuclear installations atomic energy control instruments combustion control instruments airplane or spaceship instruments transportation instruments traffic signal instruments life su...

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