583
I
2
C Bus (IIC)
Chapter 18
Preliminary User’s Manual U17566EE1V2UM00
(2)
IICSn - IICn status registers
The IICSn registers indicate the status of the I
2
Cn bus.
Access
This register can only be read in 8-bit or 1-bit units.
Address
<base> + 6
H
Initial Value
00
H
. This register is cleared by any reset.
Note
Any bit manipulation instruction targetting this register also clears this bit.
7
6
5
4
3
2
1
0
MSTSn
ALDn
EXCn
COIn
TRCn
ACKDn
STDn
SPDn
R
R
R
R
R
R
R
R
MSTSn
Master device status
0
Slave device status or communication stand-by status
1
Master device communication status
Condition for clearing (MSTSn = 0)
Condition for setting (MSTSn = 1)
•
When a stop condition is detected
•
When the ALDn = 1 (arbitration loss)
•
Cleared by LRELn = 1 (communication save)
•
When the IICEn bit changes from 1 to 0 (operation
stop)
•
After reset
•
When a start condition is generated
ALDn
Arbitration loss detection
0
This status means either that there was no arbitration or that the arbitration result was a “win”.
1
This status indicates the arbitration result was a “loss”. The MSTSn bit is cleared.
Condition for clearing (ALDn = 0)
Condition for setting (ALDn = 1)
•
Automatically cleared after the IICSn register is
read
Note
•
When the IICEn bit changes from 1 to 0 (operation
stop)
•
After reset
•
When the arbitration result is a “loss”.
EXCn
Detection of extension code reception
0
Extension code was not received.
1
Extension code was received.
Condition for clearing (EXCn = 0)
Condition for setting (EXCn = 1)
•
When a start condition is detected
•
When a stop condition is detected
•
Cleared by LRELn = 1 (communication save)
•
When the IICEn bit changes from 1 to 0 (operation
stop)
•
After reset
•
When the higher four bits of the received address
data are either “0000” or “1111” (set at the rising
edge of the eighth clock).
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