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Chapter 4
Clock Generator
Preliminary User’s Manual U17566EE1V2UM00
(5)
PCC - Processor clock control register
The 8-bit PCC register controls the CPU clock. This register can be changed
only once after reset or power save mode release.
Access
This register can be read/written in 8-bit units.
Writing to this register is protected by a special sequence of instructions.
Please refer to
“PHCMD - Command protection register” on page 140
for
details.
Address
FFFF F828
H
.
Insitial Value
10
H
. The register is initialized by any reset.
7
6
5
4
3
2
1
0
FRC
0
MFRC
CLS
0
SOSCP
CKS1
CKS0
R/W
R
a
a)
These bits may be written, but write is ignored.
R/W
R
a
R
a
R/W
R/W
R/W
Table 4-7
PCC register contents (1/2)
Bit position
Bit name
Function
7
FRC
Sub oscillator circuit: Control of internal return resistance
0: Resistor connected.
1: Resistor disconnected.
Set FRC only to 1, if the sub oscillator is not used.
5
MFRC
Main oscillator circuit: Control of internal return resistance
0: Resistor connected.
1: Resistor disconnected.
Do not change the initial setting. To ensure correct operation of the main oscillator,
the internal feed-back resistor must remain connected.
4
CLS
Processor clock source monitor flag:
0: Main oscillator operation—source can be the output of main oscillator, PLL, or
SSCG (selection through CKS[1:0]). The main oscillator is enabled by the
internal firmware.
1: Sub clock operation: 32 KHz sub or 240 KHz ring oscillator (selection through
bit SOSCP). This is the default after reset.
It is not possible to set this bit to 1 by writing to the register.
On Sub-WATCH release, the CLS bit is set to the state of PSM.OSCDIS. This is the
only way to set CLS to 1, which means, the main oscillator remains stopped and the
CPU is supplied with the sub clock chosen by SOSCP.
CLS is automatically cleared when the processor clock source is changed by writing
to PCC.CKS[1:0].
If CLS is 1, the bits CKS[1:0] have no meaning.
2
SOSCP
Sub clock selection:
0: ring oscillator is used for sub clock operation.
1: sub oscillator is used for sub clock operation.
This setting takes effect when bit CLS is 1.
Caution:
Do not specify the sub oscillator, if the sub oscillator is not enabled or
not connected.
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