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Chapter 11
16-bit Timer/Event Counter P (TMP)
Preliminary User’s Manual U17566EE1V2UM00
(4)
TPnIOC1 - TMPn I/O control register 1
The TPnIOC1 register is an 8-bit register that controls the valid edge of the
capture trigger input signals (TIPn0, TIPn1 pins).
Access
This register can be read/written in 8-bit or 1-bit units.
Address
<base> + 3
H
Initial Value
00
H
. This register is initialized by any reset.
Caution
1.
Rewrite the TPnIS3 to TPnIS0 bits when the TPnCTL0.TPnCE bit = 0. (The
same value can be written when the TPnCE bit = 1.) If rewriting was
mistakenly performed, clear the TPnCE bit to 0 and then set the bits again.
2.
The TPnIS3 to TPnIS0 bits are valid only in the free-running timer mode and
the pulse width measurement mode. In all other modes, a capture operation
is not possible.
7
6
5
4
3
2
1
0
0
0
0
0
TPnIS3
TPnIS2
TPnIS1
TPnIS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 11-6
TPnIOC1 register contents
Bit position
Bit name
Function
3 to 2
TPnIS[3:2]
Capture trigger input signal (TIPn1 pin) valied edge setting:
TPnIS3
TPnIS2
Capture trigger valid edge of TIPn1
0
0
No edge detection (capture operation invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
1 to 0
TPnIS[1:0]
Capture trigger input signal (TIPn0 pin) valied edge setting:
TPnIS1
TPnIS0
Capture trigger valid edge of TIPn0
0
0
No edge detection (capture operation invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
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