258
Chapter 7
Bus and Memory Control (BCU, MEMC)
Preliminary User’s Manual U17566EE1V2UM00
(3)
Bus access
The number of CPU clocks necessary for accessing each resource –
independent of the bus width – is as follows:
7.2.6
Boundary operation conditions
The microcontroller device has the following boundary operation conditions:
(1)
Program space
Instruction fetches from the internal peripheral I/O area are inhibited and yield
NOP operations.
If a branch instruction exists at the upper limit of the internal RAM area, a pre-
fetch operation (invalid fetch) that straddles over the internal peripheral I/O
area does not occur.
(2)
Data space
The microcontroller device is provided with an address misalign function.
By this function, data of any format (word: 32 bit, halfword: 16 bit, byte: 8 bit)
can be placed to any address in memory, even though the address is not
aligned to the data format (that means address 4n for words, address 2n for
halfwords).
• Unaligned halfword data access
When the LSB of the address is A0 =1, two byte accesses are performed.
• Unaligned word data access
When the LSB of the address is A0 =1, two byte and one halfword accesses
are performed. In total it takes 3 bus cycles.
– When the LSBs of the address are A[1:0] =10
B
, two halfword accesses
are performed.
Note
Accessing data on misaligned addresses takes more than one bus cycle to
complete data read/write. Consequently, the bus efficiency will drop.
Table 7-4
Bus priority order
Priority
External bus cycle
Bus master
High
DMA cycle
DMA Controller
Operand data access
CPU
Low
Instruction fetch
CPU
Table 7-5
Number of bus access clocks
Bus cycle configuration
Internal RAM
External I/O
External
memory
Instruction fetch
Normal access
1
a
a)
In case of contention with data access, the instruction fetch from internal RAM
takes 2 clocks.
–
2
b
Branch
1
–
2
b
Operand data access
1
3
b
b)
This is the minimum value.
2
b
electronic components distributor
