369
16-bit Timer/Event Counter P (TMP)
Chapter 11
Preliminary User’s Manual U17566EE1V2UM00
(c) TMPn I/O control register 0 (TPnIOC0)
(d) TMPn I/O control register 2 (TPnIOC2)
(e) TMPn counter read buffer register (TPnCNT)
The count value of the 16-bit counter can be read by reading the TPnCNT
register.
(f) TMPn capture/compare register 0 (TPnCCR0)
If D
0
is set to the TPnCCR0 register, the counter is cleared and a compare
match interrupt request signal (INTTPnCC0) is generated when the
number of external event counts reaches (D
0
+ 1).
(g) TMPn capture/compare register 1 (TPnCCR1)
Usually, the TPnCCR1 register is not used in the external event count
mode. However, the set value of the TPnCCR1 register is transferred to the
CCR1 buffer register. When the count value of the 16-bit counter matches
the value of the CCR1 buffer register, a compare match interrupt request
signal (INTTPnCC1) is generated.
Therefore, mask the interrupt signal by using the interrupt mask flag
(TPnCCMK1).
Note
TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0)
are not used in the external event count mode.
0
0
0
0
0/1
TPnIOC0
0: Di
sab
le TOPn0 pin o
u
tp
u
t
0: Di
sab
le TOPn1 pin o
u
tp
u
t
1: En
ab
le TOPn1 pin o
u
tp
u
t
S
etting of o
u
tp
u
t level with
oper
a
tion of TOPn1 pin
di
sab
led
0: Low level
1: High level
0/1
0
0
TPnOE1
TPnOL0
TPnOE0
TPnOL1
0
0
0
0
0/1
TPnIOC2
S
elect v
a
lid edge
of extern
a
l event
co
u
nt inp
u
t
0/1
0
0
TPnEE
S
0 TPnET
S
1 TPnET
S
0
TPnEE
S
1
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