264
Chapter 7
Bus and Memory Control (BCU, MEMC)
Preliminary User’s Manual U17566EE1V2UM00
The following setups are recommended for VSWC:
Table 7-10
Recommended timing for internal bus
System
clock
a
f
VBCLK
a)
When deriving the system clock from the modulated clock of the SSCG, the maximum clock deter-
mines the correct register setting.
≤
16 MHz
≤
25 MHz
≤
33 MHz
≤
50 MHz
≤
66 MHz
≤
75 MHz
SUWL
0
0
1
1
1
1
VSWL
0
1
1
2
3
4
VSWC
00
H
01
H
11
H
12
H
13
H
14
H
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