419
16-bit Timer/Event Counter P (TMP)
Chapter 11
Preliminary User’s Manual U17566EE1V2UM00
(e) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with
the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TPnOPT0
register. To accurately detect an overflow, read the TPnOVF bit when it is 1,
and then clear the overflow flag by using a bit manipulation instruction.
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1,
and clear it with the CLR instruction. If 0 is written to the overflow flag
without checking if the flag is 1, the set information of overflow may be
erased by writing 0 ((ii) in the above chart). Therefore, software may judge
that no overflow has occurred even when an overflow actually has
occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow
when the overflow flag is cleared to 0 with the CLR instruction, the overflow
flag remains set even after execution of the clear instruction.
(i) Oper
a
tion to write 0 (witho
u
t conflict with
s
etting)
(iii) Oper
a
tion to cle
a
r to 0 (witho
u
t conflict with
s
etting)
(ii) Oper
a
tion to write 0 (conflict with
s
etting)
(iv) Oper
a
tion to cle
a
r to 0 (conflict with
s
etting)
0 write
s
ign
a
l
Overflow
s
et
s
ign
a
l
Regi
s
ter
a
cce
ss
s
ign
a
l
Overflow fl
a
g
(TPnOVF
b
it)
Re
a
d
Write
0 write
s
ign
a
l
Overflow
s
et
s
ign
a
l
Regi
s
ter
a
cce
ss
s
ign
a
l
Overflow fl
a
g
(TPnOVF
b
it)
Re
a
d
Write
0 write
s
ign
a
l
Overflow
s
et
s
ign
a
l
0 write
s
ign
a
l
Overflow
s
et
s
ign
a
l
Overflow fl
a
g
(TPnOVF
b
it)
Overflow fl
a
g
(TPnOVF
b
it)
L
H
L
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