293
Bus and Memory Control (BCU, MEMC)
Chapter 7
Preliminary User’s Manual U17566EE1V2UM00
(2)
Read operation with address setup wait states and idle state insertion
Figure 7-18
Reading page ROM with address setup wait states and idle state
insertion
Register settings:
• BCTm.BTk0 = 1 (connected external device is page ROM)
• ASC.ACk[1:0] = 01
B
(one address setup wait state inserted)
• DWCm.DWk[2:0] = 000
B
(no programmable data wait states for off-page
access inserted)
• PRC.PRW[2:0] = 000
B
(no programmable data wait states for on-page
access inserted)
• BCC.BCk[1:0] : see
Figure 7-18
Note
1.
The circles indicate the sampling timing.
2.
The broken line indicates the high-impedance state (bus is not driven).
TA
S
W
Off-p
a
ge
a
ddre
ss
D
a
t
a
WAIT (inp
u
t)
D[15:0] (I/O)
D[7:0] (I/O)
WR (o
u
tp
u
t)
RD (o
u
tp
u
t)
C
S
k (o
u
tp
u
t)
A[2
3
:0] (o
u
tp
u
t)
BCLK
D
a
t
a
On-p
a
ge
a
ddre
ss
TA
S
W
T2
T1
TO2
TI
TO1
BCC.BCk[1:0]
00B
01B
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