846
Chapter 24
Sound Generator (SG)
Preliminary User’s Manual U17566EE1V2UM00
(2)
SG0FL - SG0 frequency low register
The 16-bit SG0FL register is used to specify the target value for the PWM
frequency. It holds the target value for the 9-bit counter SG0FL.
Access
This register is can be read/written in 16-bit units. It cannot be written if bit
SG0CTL.PWR = 0.
The SG0FL register can also be read/written together with the SG0FH register
by 32-bit access via the SG0F register.
Address
<base>
Initial Value
0000
H
. This register is cleared by any reset.
For the calculation of the resulting PWM frequency refer to
“PWM calculations“
on page 852
.
The value written to SG0FL defines also the reference value for the maximum
sound amplitude (100% PWM duty cycle). A 100 % duty cycle (continually
high) will be generated if the SG0PWM value is higher than the SG0FL value.
For details see
“PWM calculations“ on page 852
).
Note
1.
The bits SG0FL[15:9] are not used.
2.
The maximum value to be written is 510 (01FE
H
). This yields a PWM
frequency of 31.3 KHz. The minimum value to be written depends on the
capability of the external circuit. A value of 255 (00FF
H
) would yield a PWM
frequency of 62.5 KHz.
3.
The value read from this register does not necessarily reflect the current
PWM frequency, because this frequency is determined by the frequency
compare buffer value. The buffer might not be updated yet.
For details see
“Updating the frequency buffer values“ on page 849
.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Counter SG0FL target value
R
R
R
R
R
R
R
R/W
electronic components distributor
