NEC V850E/Dx3, Preliminary User'S Manual

Page: 174 / 930

174
Chapter 4 Clock Generator
Preliminary User’s Manual U17566EE1V2UM00
T
a
b
le 4-
29
S
tat
u
s
o
f o
scil
lat
o
rs a
n
d
C
lo
c
k
G
e
n
e
ra
to
r o
u
tp
u
t c
lo
c
ks (
1
/3
)
Ma
cr
o
Cloc
k
si
gnal
Co
nditi
on
Res et
Res et
rele as e
Norm al
IDLE
IDLE
rele as e
STOP
STOP
rele as e
WA T CH
WA T CH
rele as e
Sub-WA TCH
Sub-WA TCH
rele as e
Os
cil
lator
s
M
a
in
-o
s
c
–
O
SCDIS=
0
n
.a
.
o
n
o
n
sto
p
on
on
o
n
st
op
on
O
S
CDIS=
1
s
top
s
to
p
n
.a.
s
to
p
n
.a
.
s
to
p
Sub
-os
c
–
SOST
P=1
n
.a
.
on
on
sto
p
on
on
on
SOST
P=0
o
n
o
n
R
ing
-os
c
–
R
O
S
TP=1
n.a
.
on
on
sto
p
on
sto
p
on
st
op
on
R
O
STP=0
o
n
o
n
o
n
o
n
SSCG
/PLL
SSCG
–
–
st
b
y
sc
en
sc
e
n
st
b
y
st
b
y
st
b
y
PLL
–
–
p
lle
n
p
llen
Cloc
k G
e
nerato
r outpu
t c
loc
ks
CPU sy
st
em
cl
oc
k
VBCLK
CL
S/CKS =
000
B
n.a
.
MOCL
K
of
f
MOCL
K
of
f
MO
C
L
K
off
MO
C
L
K
off
MO
C
L
K
CL
S/CKS =
001
B
S
S
C
C
L
K
n
.a
.n
.a
.n
.a
.n
.a
.
CL
S/CKS =
01x
B
PLLC
L
K
n.a
.
n.a
.
n.
a.
n.
a.
CL
S/CKS =
1x
x
B
off
R
O
C
LK
SBC
LK
n.a
.
n.a
.
n.
a.
SB
C
L
K
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