883
On-Chip Debug Unit
Chapter 28
Preliminary User’s Manual U17566EE1V2UM00
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External RESET
External reset by the RESET pin sets OCDM.OCDM0 = 1, i.e. the pins are
defined as N-Wire interface pins. If connected the debugger can communicate
with the on-chip debug unit and take over CPU control.
During and after RESET the pins P05, P52…P55 are configured as follows:
• DRST, DDI, DCK, DMS are inputs.
• DDO is output, but in high impedance state as long as DRST = 0.
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Other resets
Resets from all other reset sources do not affect the pins P05, P52...P55.
An internal pull-down resistor is provided for the pin P05/DRST. During and
after any reset the resistor is connected to P05/DRST, ensuring that the
N-Wire interface is kept in reset state, if no debugger is connected. The
internal pull-down resistor is connected by reset from any source and can be
disconnected via the port configuration register bit PFC0.PDC05.
The DRST signal depicts the N-Wire interface reset signal. If DRST = 0 the
on-chip debug unit is kept in reset state and does not impact normal controller
operation. DRST is driven by the debugger, if one is connected. The debugger
may start communication with the controller by setting DRST = 1.
Pin configuration
• In N-Wire debug mode the configuration of the N-Wire interface pins can not
be changed by the pin configuration registers. The registers contents can be
changed but will have no effect on the pin configuration.
• In N-Wire debug mode the output current limiting function of the DDO pin is
disabled. By this means the port pin provides maximum driver capability in
order to maximize the transmission data rate to the N-Wire debugger. Note
that the settings of the port registers are not affected.
Note
This chapter describes the N-Wire interface control only. An additional security
function decides, if the debugger access to the microcontroller is granted or
not. Please refer to
“Code Protection and Security” on page 339
.
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