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NEC V850E/Dx3, Preliminary User'S Manual


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Chapter 8 

DMA Controller (DMAC) 

Preliminary User’s Manual U17566EE1V2UM00

Figure 8-2

Example of forcible interruption of DMA transfer

Caution

The resumed DMA transfer after NMI interruption cannot be executed with new 
settings. New settings for a DMA transfer can be validated either after the end 
of the current transfer or after the transfer has been forcibly terminated by 
setting the INITn bit of the DCHCn register.

8.10 Forcible Termination

In addition to the forcible interruption operation by means of the NMI input, 
DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register. 
The following is an example of the operation of a forcible termination.

Figure 8-3

 shows a block transfer of channel 3 which begins during the DMA 

block transfer of DMA channel 2. The block transfer of DMA channel 2 is 
forcibly terminated by setting the INIT2 bit of its DCHC2 control register.

Figure 8-3

DMA transfer forcible termination example 1 

DMA transfer stop

DMA transfer

DMA transfer

DMA transfer stop

EN0 bit of DCHC0 register

NMI (input)

Forcible
interruption

Forcible
interruption

Transfer
restart

DMA Transfer

Request CH2

DMA Transfer

Request CH3

CPU

DMA3

DMA3

DMA3 DMA3 CPU

CPU

CPU

CPU

CPU

DMA2

DMA2

DMA2

DMA2 DMA2

CPU

CPU

EN3 bit = 1
TC3 bit = 0

EN3 bit

 0

TC3 bit 

 1

Set register

EN2 bit = 1
TC2 bit = 0

Set register

Set register

EN2 bit 

 0

TC2 bit = 0

DMA channel 3 terminal count

DMA channel 3 transfer begins

DMA channel 2 transfer is forcibly terminated 
and the bus is released

DSAL2, DSAH2,
DDAL2, DDAH2

DSAL3, DSAH3,
DDAL3, DDAH3

DCHC2
(INIT2 bit = 1)

→

→

→

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Summary of Contents for V850E/Dx3

Page 1: ...Hardware PD70F3420 PD703420 PD70F3421 PD703421 PD70F3422 PD703422 PD70F3423 PD70F3424 PD70F3425 PD70F3426 PD70F3427 Document No U17566EE1V2UM00 Date Published 18 7 06 NEC Electronics 2006 Printed in...

Page 2: ...2 V850E Dx3 Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 3: ...inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices...

Page 4: ...ponsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and...

Page 5: ...nics s willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics...

Page 6: ...408 588 6130 800 729 9288 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 Sucursal en Espa a Madrid Spain Tel 091 504 27 87 Fax 091 504 28 60 Succursale Fran aise...

Page 7: ...is high order column right is low order column Active low notation xxx pin or signal name is over scored or xxx slash before signal name Memory map address High order at high stage and low order at l...

Page 8: ...8 V850E Dx3 Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 9: ...t selection 50 2 3 Port Types Diagrams 52 2 4 Port Group Configuration 56 2 4 1 Port group configuration lists 56 2 4 2 Alphabetic pin function list 65 2 4 3 External memory interface of PD70F3427 71...

Page 10: ...e 115 3 4 1 CPU address space and physical address space 115 3 4 2 Program and data space 117 3 5 Memory 119 3 5 1 Memory areas 119 3 5 2 Recommended use of data address space 123 3 6 Write Protected...

Page 11: ...3 4 xxIC Maskable interrupts control register 210 5 3 5 IMR0 to IMR5 Interrupt mask registers 214 5 3 6 ISPR In service priority register 216 5 3 7 Maskable interrupt status flag ID 216 5 3 8 External...

Page 12: ...external devices 259 7 2 8 External bus mute function 259 7 3 Registers 260 7 3 1 BCU registers 261 7 3 2 Memory controller registers PD70F3427 only 271 7 4 Page ROM Controller 279 7 5 Configuration...

Page 13: ...ansfer Start Factors 325 8 9 Forcible Interruption 325 8 10 Forcible Termination 326 8 11 DMA Transfer Completion 327 8 12 Transfer Mode 328 8 12 1 Single transfer mode 328 8 12 2 Block transfer mode...

Page 14: ...27 11 6 2 Count jitter for PCLK4 to PCLK7 count clocks 427 Chapter 12 16 bit Interval Timer Z TMZ 429 12 1 Overview 429 12 1 1 Description 430 12 1 2 Principle of operation 430 12 2 TMZ Registers 431...

Page 15: ...figuration 508 16 3 UARTA Registers 510 16 4 Interrupt Request Signals 518 16 5 Operation 519 16 5 1 Data format 519 16 5 2 SBF transmission reception format 521 16 5 3 SBF transmission 523 16 5 4 SBF...

Page 16: ...ers 571 17 7 3 Baud rate calculation 572 Chapter 18 I2C Bus IIC 573 18 1 Features 573 18 2 I2C Pin Configuration 574 18 3 Configuration 575 18 4 IIC Registers 578 18 5 I2C Bus Pin Functions 593 18 6 I...

Page 17: ...frame 653 19 3 Functions 654 19 3 1 Determining bus priority 654 19 3 2 Bit stuffing 654 19 3 3 Multi masters 655 19 3 4 Multi cast 655 19 3 5 CAN sleep mode CAN stop mode function 655 19 3 6 Error c...

Page 18: ...mode 728 19 12 2 CAN stop mode 730 19 12 3 Example of using power saving modes 731 19 13 Interrupt Function 732 19 14 Diagnosis Functions and Special Operational Modes 733 19 14 1 Receive only mode 7...

Page 19: ...816 22 3 1 Common signals and segment signals 816 22 3 2 Activation of LCD segments 818 22 4 Display Example 818 Chapter 23 LCD Bus Interface LCD I F 823 23 1 Overview 823 23 1 1 Description 824 23 1...

Page 20: ...860 Chapter 26 Reset 861 26 1 Overview 861 26 1 1 General reset performance 861 26 1 2 Reset at power on 865 26 1 3 External RESET 866 26 1 4 Reset by Watchdog Timer 867 26 1 5 Reset by Clock Monitor...

Page 21: ...Connection to N Wire Emulator 886 28 4 1 KEL connector 886 28 5 Restrictions and Cautions on On Chip Debug Function 890 Appendix A Special Function Registers 891 Appendix B Registers Access Times 911...

Page 22: ...22 Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 23: ...f sophisticated peripheral functions and CAN network support is required 1 V850E CPU The V850E CPU core is a RISC processor Through the use of basic instructions that can be executed in one clock peri...

Page 24: ...registers 32 bits each Instruction set V850E compatible with V850 plus additional powerful instructions for reducing code and increasing execution speed Signed multiplication 16 bits 16 bits 32 bits...

Page 25: ...3427 up to 25 2 MHz PD70 F 3420 PD70 F 3421 PD70 F 3422 PD70F3423 Peripheral frequency range up to 16 MHz Main crystal frequency range main oscillator 4 MHz Sub oscillator 32 KHz typ Ring oscillator 2...

Page 26: ...mers 16 bit multi purpose timer event counter TMP 4 channels 16 bit multi purpose timer counter TMG 3 channels 16 bit multi purpose timer counter TMZ 10 channels PD70F3424 PD70F3425 PD70F3426 PD70F342...

Page 27: ...70F3424 PD70F3425 PD70F3426 PD70F3427 84 sources PD70 F 3420 PD70 F 3421 PD70 F 3422 PD70F3423 Software exceptions 32 sources Exception trap 2 sources ROM Correction Number of channels 8 channels by D...

Page 28: ...none 128 KB none ROM none 384 KB none 256 KB none 128 KB RAM 60 KB 60 KB 24 KB a 32 KB 24 KB 20 KB 16 KB 12 KB 6 KB External memory interface provided DMA 4 ch Operating clock Main oscillator with SSC...

Page 29: ...er 6 channels LCD Controller Driver none 40 x 4 LCD Bus Interface provided Auxiliary frequency output provided On Chip debug provided Operating voltage 3 5 V to 5 5 V c Package 208 pin QFP 144 pin QFP...

Page 30: ...21 to SM24 SM31 to SM34 SM61 to SM64 SM51 to SM54 Note 2 Note 1 LCD C D SEG0 to SEG39 COM0 to COM3 LCD Bus I F DBD0 to DBD7 DBRD DBWR SG0 SGOA SGO SGOF AVREF ANI0 ANI11 10 bit ADC 16 12 channels 16 bi...

Page 31: ...arked as Notes in Figure 1 1 Table 1 3 Feature set differences Note Feature F3426 F3425 F3424 F3423 F3422 3422 F3421 3421 F3420 3420 1 INTP7 2 CSIB2 3 ANI12 to ANI15 4 LCD C D 5 TMZ6 to TMZ9 6 Flash 1...

Page 32: ...r TMG0 TMG2 16 bit Timer TMP0 TMP3 TIP00 TIP01 TIP10 TIP11 TIP20 TIP21 TIP30 TIP31 TOP00 TOP01 TOP10 TOP11 TOP20 TOP21 TOP30 TOP31 2 x I2 C SDA0 SDA1 SCL0 SCL1 VCMP0 VCMP1 2 x Voltage Comparator VCMPO...

Page 33: ...the building blocks their features and how to set registers in order to enable or disable specific functions The manual provides individual chapters for the building blocks These chapters are organize...

Page 34: ...20GJ A GAE QS AX 144 pin LQFP 128 KB flash UPD703421GJ A GAE QS AX 144 pin LQFP 256 KB ROM UPD70F3421GJ A GAE QS AX 144 pin LQFP 256 KB flash UPD703422GJ A GAE QS AX 144 pin LQFP 384 KB ROM UPD70F3422...

Page 35: ...Terms on page 39 Features summary Number of ports and port groups 5V I O Can be used as 3V I O with degraded electrical parameters Please refer to the Electrical Target Specification 24 high drive po...

Page 36: ...P07 Port group 8 P80 P87 to Port group 3 P30 to P37 Port group 1 P16 P17 Port group 4 P40 to P47 Port group 5 P50 to P57 Port group 6 P60 to P67 Port group 9 P90 P97 to Port group 10 P100 P107 to Por...

Page 37: ...data UARTA1 transmit receive data I2 C1 data clock line LCD controller segment signal output PD70 F 3420 PD70 F 3421 PD70 F 3422 PD70F3423 only Timer TMG2 channels Timer TMP0 to TMP3 channels 4 8 bit...

Page 38: ...ta 9 8 bit input output LCD Bus I F data lines LCD controller segment common signal output PD70 F 3420 PD70 F 3421 PD70 F 3422 PD70F3423 only 10 8 bit input output Timer TMP0 to TMP3 channels LCD Bus...

Page 39: ...functions for example as the input output pin of on chip peripherals The corresponding pin name depends on the selected function For example pin INTP0 denotes the pin for one of the external interrupt...

Page 40: ...the following registers are used n 0 to 14 Table 2 2 Registers for port group configuration Register name Shortcut Function Port mode register PMn Pin function configuration Port mode control register...

Page 41: ...tings is given in the table below Table 2 3 Pin function configuration overview Function Registers I O OCDM PLCDC PMC PFC PM Port mode output 0 0 0 X 0 O Port mode input X 1 I Alternative output 1 mod...

Page 42: ...s see Port Group Configuration on page 56 Initial Value FFH or FFFFH This register is initialized by any reset 7 6 5 4 3 2 1 0 PMn7 PMn6 PMn5 PMn4 PMn3 PMn2 PMn1 PMn0 R W R W R W R W R W R W R W R W 1...

Page 43: ...n 8 bit and 1 bit units Address see Port Group Configuration on page 56 Initial Value PFC0 20H other PFCn 00H This register is initialized by any reset 7 6 5 4 3 2 1 0 PMCn7 PMCn6 PMCn5 PMCn4 PMCn3 PM...

Page 44: ...is register is initialized by any reset Note If PLCDCn PLCDCnm 1 the settings of the bits m in registers PMn PMCn and PFCn are neglected 7 6 5 4 3 2 1 0 PLCDCn7 PLCDCn6 PLCDCn5 PLCDCn4 PLCDCn3 PLCDCn2...

Page 45: ...to On Chip Debug Unit on page 877 Access This register can be read written in 8 bit and 1 bit units Address FFFF F9FCH Initial Value 00H 01H After Power On Clear reset the normal operation mode is se...

Page 46: ...in input mode PMn PMnm 1 The read input value is determined by the port pins Note The value written to register Pn is retained until a new value is written to register Pn Data is written to or read fr...

Page 47: ...sters can also be read in 16 bit units Address see Port Group Configuration on page 56 Initial Value 00H or 0000H This register is cleared by any reset 7 6 5 4 3 2 1 0 PPRn7 PPRn6 PPRn5 PPRn4 PPRn3 PP...

Page 48: ...ICCn Port input characteristic control register The 8 bit PICCn register selects between Schmitt Trigger or non Schmitt Trigger input characteristics Access This register can be read written in 8 bit...

Page 49: ...on page 56 Initial Value 00H This register is cleared by any reset If open drain emulation is enabled the output function of concerned pin is automatically enabled as well independently of the PMn PMn...

Page 50: ...r the peripheral functions CSIB0 I2C0 and I2C1 Access This register can be read written in 8 bit units Address FFFF F720H Initial Value 01H This register is initialized by any reset 7 6 5 4 3 2 1 0 0a...

Page 51: ...ster is initialized by any reset 7 6 5 4 3 2 1 0 0a a These bits must not be changed 0a PFSR35 PFSR34 0a 0a 0a 1a R W R W R W R W R W R W R W R W Table 2 17 PFSR3 register contents Bit position Bit na...

Page 52: ...different types This chapter presents the block diagrams of all port types 1 Port type M Figure 2 2 Block diagram port type M PICCnm PMCnm PMnm Pnm 0 1 1 0 0 1 ALT1 OUT PFCnm ALT2 OUT ALT IN PODCnm P...

Page 53: ...er to Port type R on page 55 3 The analog filter is provided only for alternative external interrupt ports P00 04 P06 P07 The PD70F3424 PD70F3425 PD70F3426 PD70F3427 provides an additional analog filt...

Page 54: ...00 2 Port type Q Figure 2 3 Block diagram port type Q PMCnm PMnm Pnm 0 1 1 0 0 1 ALT1 OUT PFCnm ALT2 OUT internal RESET PODCnm Pnm PRD PICCnm PDSCnm LCD Bus I F read PPRRD ENABLE LCD Bus I F write ENA...

Page 55: ...M OCDM0 1 the corresponding pins are operating in on chip debug mode The pins are automatically set as input or output pins respectively Setting of bits PMn PMnm is not necessary For more details refe...

Page 56: ...0 on page 65 In Table 2 58 on page 97 it is listed how the pin functions change if the microcontroller is reset or if it is in one of the standby modes In the subsections for every port group the sett...

Page 57: ...INTP6 M 1 P16 SDA0 SDA0 M P17 SCL0 SCL0 M 2 P20 SDA1 SEG0 SDA1 M P21 SCL1 SEG1 TIG02 SCL1 M P22 SEG2 TIG03 M P23 SEG3 TIG04 M P24 SEG4 TIG11 M P25 SEG5 TIG12 M P26 SEG6 TIG13 M P27 SEG7 TIG14 M 3 P30...

Page 58: ...CL0 M P65 SDA0 TOP30 SEG17 TIP30 SDA0 M P66 SEG18 TIP21 M P67 TOP31 SEG19 TIP31 M 7 P70 ANI0 B P71 ANI1 B P72 ANI2 B P73 ANI3 B P74 ANI4 B P75 ANI5 B P76 ANI6 B P77 ANI7 B P78 ANI8 B P79 ANI9 B P710 A...

Page 59: ...M P102 TOP20 M P103 TOP21 M P104 DBRD SEG35 M P105 DBWR SEG34 SIB0 M P106 SOB0 SEG33 M P107 SCKB0 SEG32 SCKB0 M 11 P110 SM11 M P111 SM12 M P112 SM13 M P113 SM14 M P114 SM21 M P115 SM22 M P116 SM23 M...

Page 60: ...equipped with high drive buffers for stepper motor control Table 2 19 Port group list for PD70F3424 PD70F3425 PD70F3426 PD70F3427 1 5 Port group name Port name Alternative outputs ALT1_OUT ALT2_OUT L...

Page 61: ...TOP31 TOG23 TIG23 M P37 TOP11 TOG24 TIG24 M 4 P40 SIB0 M P41 SOB0 M P42 SCKB0 SCKB0 M P43 SIB1 M P44 SOB1 M P45 SCKB1 SCKB1 M P46 CRXD0 M P47 CTXD0 M 5 P50 FOUT SGOA INTP7 M P51 SGO M P52 DDI R P53 DD...

Page 62: ...73 ANI3 B P74 ANI4 B P75 ANI5 B P76 ANI6 B P77 ANI7 B P78 ANI8 B P79 ANI9 B P710 ANI10 B P711 ANI11 B P712 B P713 B P714 B P715 B 8 P80 SIB2 M P81 SOB2 M P82 SCKB2 SCKB2 M P83 M P84 M P85 FOUT M P86 T...

Page 63: ...1 M P115 SM22 M P116 SM23 M P117 SM24 M Note Port group 11 is equipped with high drive buffers for stepper motor control 12 P120 SM51 M P121 SM52 M P122 SM53 M P123 SM54 M P124 SM61 M P125 SM62 M P126...

Page 64: ...e Port group 13 is equipped with high drive buffers for stepper motor control 14a P140 BCLK M P141 BE2 M P142 BE3 M MEM I Fa A 23 0 CS0 CS1 CS3 CS4 WR RD BE0 BE1 D 15 0 a PD70F3427 only Table 2 19 Por...

Page 65: ...2 to 15 P712 to P715 AVDD ADC supply voltage no ports AVREF ADC reference voltage input no ports AVSS ADC ground no ports BE0 BE1 O External memory interface byte enable signals 0 1 no ports BE2 O Ext...

Page 66: ...DRST I N Wire debug interface reset P05 DVDD50 LCD Bus I F supply voltage no ports DVSS50 LCD Bus I F supply ground no ports DVDD51 LCD Bus I F D 31 16 ports supply voltage no ports DVSS51 LCD Bus I F...

Page 67: ...P16 P65 SDA1 I O I2 C1 data line P20 P30 SEG0 to SEG7 O LCD segment lines 0 to 39 P20 to P27 SEG8 to SEG11 P34 to P37 SEG12 to SEG19 P60 to P67 SEG20 to SEG22 P45 to P43 SEG23 to SEG26 P83 to P80 SEG...

Page 68: ...motor 6 output sin P124 SM62 O Stepper motor 6 output sin P125 SM63 O Stepper motor 6 output cos P126 SM64 O Stepper motor 6 output cos P127 SMVDD50 SMVDD51 Stepper Motor Controller Driver supply volt...

Page 69: ...TMP1 channel 1 output P37 P63 TOP20 O Timer TMP2 channel 0 output P102 TOP21 O Timer TMP2 channel 1 output P35 P103 TOP30 O Timer TMP3 channel 0 output P65 TOP31 O Timer TMP3 channel 1 output P36 P67...

Page 70: ...ote Alternative input functions of CSIB0 UART0 and UART1 are provided on two pins each Thus you can select on which pin the alternative function should appear Refer to Alternative input selection on p...

Page 71: ...it changes the interface from 16 to 32 bit mode All other bus interface signals are available via group 14 also usable as 3 bit I O port and the permanent MEM I F group Table 2 21 External memory inte...

Page 72: ...Level Detection Configuration on page 218 Table 2 22 Port group 0 pin functions and port types Pin functions in different modes Pin function after reset Port type Port mode PMCnm 0 Alternative mode P...

Page 73: ...to connect disconnect the internal pull down resistor at pin P05 DRST X X X X X OCDM FFFF F9FCH 00H 01H c c Depends on the reset source Refer to OCDM On chip debug mode register on page 45 and to On...

Page 74: ...functions and port types Pin functions in different modes Pin function after reset Port type Port mode PMCnm 0 Alternative mode PMCnm 1 Output mode PMnm 0 Input mode PMnm 1 P16 I O SDA0a a In I2 C fun...

Page 75: ...SDA1b SDA1 SEG0a P20 I M P21 I O SCL1b TIG02 SCL1 SEG1a P21 I M P22 I O TIG03 SEG2a P22 I M P23 I O TIG04 SEG3a P23 I M P24 I O TIG11 SEG4a P24 I M P25 I O TIG12 SEG5a P25 I M P26 I O TIG13 SEG6a P26...

Page 76: ...ch pin the alternative function should appear If alternative functions SDA1 SCL1 are used at P30 31 make sure to set also PFSR0 PFSR05 1 Refer to Alternative input selection on page 50 Table 2 28 Port...

Page 77: ...MC32 PMC31 PMC30 PFC3 FFFF F466H 00H PFC37 PFC36 PFC35 PFC34 X X X PFC30 PLCDC3a a PD70 F 3420 PD70 F 3421 PD70 F 3422 PD70F3423 only FFFF F346H 00H PLCDC37 PLCDC36 PLCDC35 PLCDC34 PLCDC33 PLCDC32 X X...

Page 78: ...MCnm 0 Alternative mode PMCnm 1 LCD mode PLCDCnm 1 a Output mode PMnm 0 Input mode PMnm 1 P40 I O SIB0 P40 I M P41 I O SOB0 P41 I M P42 I O SCKB0 SCKB0 P42 I M P43 I O SIB1 SEG22a P43 I M P44 I O SOB1...

Page 79: ...us you can select on which pin the alternative function should appear Refer to Alternative input selection on page 50 Table 2 32 Port group 5 pin functions and port types Pin functions in different mo...

Page 80: ...X X X PMC51 PMC50 PFC5 FFFF F46AH 00H PFC57 X X X X X X PFC50 OCDM FFFF F9FCH 00H 01H 0 0 0 0 0 0 0 OCDM0 P5 FFFF F40AH 00H P57 P56 P55 P54 P53 P52 P51 P50 PPR5 FFFF F3CAH 00H PPR57 PPR56 PPR55 PPR54...

Page 81: ...tions SDA0 SCL0 are used at P64 65 make sure to set also PFSR0 PFSR04 1 Refer to Alternative input selection on page 50 Table 2 34 Port group 6 pin functions and port types Pin functions in different...

Page 82: ...se bits must not be changed 0a PFC65 0a 0a 0a 0a X PLCDC6b b PD70 F 3420 PD70 F 3421 PD70 F 3422 PD70F3423 only FFFF F34CH 00H PLCDC67 PLCDC66 PLCDC65 PLCDC64 PLCDC63 PLCDC62 PLCDC61 PLCDC60 P6 FFFF F...

Page 83: ...ort group 7 always function in alternative input mode Table 2 36 Port group 7 pin functions and port types Pin functions in different modes Pin function after reset Port type Port mode PMCnm 0 Alterna...

Page 84: ...F44EH 00H PMC77 PMC76 PMC75 PMC74 PMC73 PMC72 PMC71 PMC70 PMC7H FFFF F44FH 00H PMC715 PMC714 PMC713 PMC712 PMC711 PMC710 PMC79 PMC78 PMC7 16 bit FFFF F44EH 0000H PMC715 to PMC78 PMC7H PMC77 to PMC70...

Page 85: ...ailable 2 The alternative input function of UART0 is provided on two pins Thus you can select on which pin the alternative function should appear Refer to Alternative input selection on page 50 Table...

Page 86: ...D70 F 3422 PD70F3423 only FFFF F350H 00H PLCDC87 PLCDC86 PLCDC85 X PLCDC83 PLCDC82 PLCDC81 PLCDC80 P8 FFFF F410H 00H P87 P86 P85 P84 P83 P82 P81 P80 PPR8 FFFF F3D0H 00H PPR87 PPR86 PPR85 PPR84 PPR83 P...

Page 87: ...tive mode PMCnm 1 LCD mode PLCDCnm 1 a Output mode PMnm 0 Input mode PMnm 1 P90 I O DBD0 SEG36a P90 I M P91 I O DBD1 SEG37a P91 I M P92 I O DBD2 SEG38a P92 I M P93 I O DBD3 SEG39a P93 I M P94 I O DBD4...

Page 88: ...utput mode PMnm 0 Input mode PMnm 1 P100 I O TOP00 TIP00 P100 I M P101 I O TOP01 P101 I M P102 I O TOP20 P102 I M P103 I O TOP21 P103 I M P104 I O DBRD SEG35a P104 I M P105 I O DBWR SIB0 SEG34a P105 I...

Page 89: ...t mode PMnm 0 Input mode PMnm 1 P110 I O SM11 P110 I M P111 I O SM12 P111 I M P112 I O SM13 P112 I M P113 I O SM14 P113 I M P114 I O SM21 P114 I M P115 I O SM22 P115 I M P116 I O SM23 P116 I M P117 I...

Page 90: ...ut mode PMnm 1 P120 I O SM51 P120 I M P121 I O SM52 P121 I M P122 I O SM53 P122 I M P123 I O SM54 P123 I M P124 I O SM61 P124 I M P125 I O SM62 P125 I M P126 I O SM63 P126 I M P127 I O SM64 P127 I M T...

Page 91: ...ort mode PMCnm 0 Alternative mode PMCnm 1 output mode PMnm 0 Input mode PMnm 1 PFCnm 0 ALT1 OUT PFCnm 1 ALT2 OUT P130 I O SM31 TOG01 TIG01 P130 I M P131 I O SM32 TOG02 P131 I M P132 I O SM33 TOG03 P13...

Page 92: ...Alternative mode PMCnm 1 Output mode PMnm 0 Input mode PMnm 1 P140 I O BCLK P140 I M P141 I O BE2 P141 I M P142 I O BE3 P142 I M Table 2 51 Port group 14 configuration registers Register Address Initi...

Page 93: ...gitally filtered inputs The inputs of the peripherals listed below are passed through a digital filter to remove noise and glitches The digital filter operates in all modes which have the PLL enabled...

Page 94: ...external input signals The filter is enabled disabled by the 16 bit registers DFEN0 and DFEN1 1 DFEN0 Digital filter enable register The 16 bit DFEN0 register enables disables the digital filter for...

Page 95: ...disabled Otherwise desired input pulses may be removed by the digital filter 1 DFENC1 SIB1 CSIB1 data inputa 2 DFENC2 SIB2 CSIB2 data inputa 3 DFENC3 SCKIB0 CSIB0 clock inputa 4 DFENC4 SCKIB1 CSIB1 c...

Page 96: ...r is enabled For an assignment of bit positions to input signals see table Table 2 57 Table 2 57 Assignment of input signals to bit positions for register DFEN1 Bit position Bit name Input signal Desc...

Page 97: ...tatus Power On Clear during P05 DRST P05 port input with internal pull down resistor all other pins Hi Z 3 state after input port mode external RESET during P05 DRST P05 port input with internal pull...

Page 98: ...f no sub oscillator crystal is connected connect XT1 to Vss and leave XT2 open Note If the overall maximum output current of a concerned pin group exceeds its maximum value the output buffer can be da...

Page 99: ...DB1 SEG37 29 P135 SM42 TOG12 89 BVDD51 144 P70 AIN0 50 BVSS50 113 P96 DB6COM2 52 P102 TOP20 82 P61 TIP01 TIG21 SEG13 134 P710 AIN10 125 XT2 87 P66 TIP21 SEG18 127 VCMP0 36 P01 INTP1 32 P06 INTP5 3 AVS...

Page 100: ...OG12 89 BVDD51 144 P70 AIN0 50 BVSS50 113 P96 DBD6 52 P102 TOP20 82 P61 TIP01 TIG21 134 P710 AIN10 125 XT2 87 P66 TIP21 127 VCMP0 36 P01 INTP1 32 P06 INTP5 3 AVSS 59 P57 TXDA1 CTXD1 143 P71 AIN1 133 P...

Page 101: ...161 P36 TIG23 TOG23 TOP31 20 P126 SM63 114 MVSS54 163 P60 TIG20 63 VSS50 25 P133 SM34 TOG04 50 P87 RXDA0 D17 89 A0 7 P113 SM14 70 D1 10 P114 SM21 SGO 81 D10 115 A19 6 P112 SM13 92 A3 88 D15 86 MVDD52...

Page 102: ...102 Chapter 2 PinFunctions Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 103: ...gital control applications a 32 bit hardware multiplier enables this CPU to support multiply instructions saturated multiply instructions bit operation instructions etc Features summary The CPU has th...

Page 104: ...hifter CPU V S B DMA control unit DMAC System controller Bus bridge BBR Instruction queue Bus control unit BCU NPB V D B V F B System registers RCU interface Standby control unit STBC Interrupt contro...

Page 105: ...r1 6 r1 7 r1 8 r1 9 r2 0 r2 1 r2 2 r2 3 r2 4 r2 5 r2 6 r2 7 r2 8 r2 9 r3 0 r3 1 3 1 0 3 1 0 Zero Register Reserved for Assembler Interrupt Stack Pointer Stack Pointer SP Global Pointer GP Text Pointe...

Page 106: ...tion r0 Zero register Always holds 0 It is used for operations using 0 and offset 0 addressing a a Registers r0 and r30 are used by dedicated instructions r1 Assembler reserved register Used for 32 bi...

Page 107: ...pt stores contents of PC EIPC 1 Status saving register during interrupt stores contents of PSW EIPSW 2 Status saving register during non maskable interrupts stores contents of PC FEPC 3 Status saving...

Page 108: ...IPC or FEPC must be saved by program because only one PC saving register for maskable interrupts and non maskable interrupts is provided respectively Caution When setting the value of any of the PC sa...

Page 109: ...ress 1 Exception processing is in progress 5 ID Indicates whether a maskable interrupt request can be acknowledged 0 Interrupts enabled 1 Interrupts disabled Note Setting this flag will disable interr...

Page 110: ...s shown in the table below Note that the SAT flag is set only when the OV flag has been set during a satu rated operation Table 3 6 Saturation processed operation result Status of operation result Fla...

Page 111: ...EIPC FEPC or CTPC use even values bit 0 0 If bit 0 is set to 1 the setting of this bit is ignored This is because bit 0 of the program counter is fixed to 0 Table 3 7 PSW saving registers Register Sh...

Page 112: ...EICC Table 3 8 ECR register contents Bit position Bit name Function 31 to 16 FECC Exception code of non maskable interrupt NMI 15 to 0 EICC Exception code of exception or maskable interrupts Table 3 9...

Page 113: ...and after the completion of interrupt servicing the execution is resumed 6 CTBP CALLT base pointer The 32 bit CALLT base pointer is used with the CALLT instruction The register content is used as a b...

Page 114: ...cks the FLMD0 pin and optionally also the FLMD1 pin to set the operation mode after reset release according to Table 3 10 Note The FLMD1 pin function is shared with the P07 pin ROM mask devices Since...

Page 115: ...h Memory on page 229 3 4 Address Space In the following sections the address space of the CPU is explained Size and addresses of CPU address space and physical address space are explained The address...

Page 116: ...0H FBFF FFFFH 0000 0000H Image Image Image Peripheral I O Physical address space x3FF FFFFH x000 0000H Image Image F800 0000H F7FF FFFFH 0800 0000H 07FF FFFFH 0400 0000H 03FF FFFFH CPU address space x...

Page 117: ...ly the lower 64 MB of the CPU address space can be used for instruction addresses When an instruction address for a branch instruction is calculated and moved to the program counter PC then bits 31 to...

Page 118: ...its only the lower 26 bits of the result are considered Therefore the addresses 0000 0000H and 03FF FFFFH are contiguous addresses This results in a wrap around of the program space Figure 3 6 Wrap ar...

Page 119: ...a The areas are briefly described below 1 Internal VFB flash area Table 3 11 summarizes the size and addresses of the ROM and flash memories which are accessible via the VFB V850 Fetch Bus Table 3 11...

Page 120: ...03FF 1000H 03FF 1FFFH 2 4 KB 03FF 2000H 03FF 2FFFH PD70F3421 12 KB 0 4 KB 03FF 0000H 03FF 0FFFH 1 8 KB 03FF 1000H 03FF 2FFFH PD70 F 3422 16 KB 0 8 KB 03FF 0000H 03FF 1FFFH 1 8 KB 03FF 2000H 03FF 3FFFH...

Page 121: ...bits A 31 26 are not considered Thus this address space can also be addressed via the area FFFF 0000H to FFFF FFFFH This has the advantage that the area can be indirectly addressed by an offset and t...

Page 122: ...rea 0FFF F000H to 0FFF FFFFH for source destination address of DMA transfer 6 Programmable peripheral I O area A 16 KB area is provided as a programmable peripheral I O area PPA The PPA can be freely...

Page 123: ...ange FFFF F800H to 0000 0000H and 0000 0000H to 0000 7FFFH The peripheral I O registers and the internal RAM is aligned to the upper bound thus the registers and a part of the RAM can be addressed via...

Page 124: ...able register Shortcut Status register For details see Clock control register CKC Peripheral command register PHCMD PHS Clock Generator on page 129 Watchdog timer clock control register WCC Processor...

Page 125: ...roys this sequence the effects of interrupts and DMA transfers have to be considered Interrupts In order to prevent any maskable interrupt to be acknowledged between the two write instructions in ques...

Page 126: ...gisters via the NPB etc Thus the figures in the below tables assume all busses VFB VDB VSB NPB are not occupied i e collision with other bus traffic is excluded 32 bit instruction data accesses to wor...

Page 127: ...flash Consecutive 1 1 1 1 Random 3a a These values include the additional clock cycle cause by the CPU s pipeline break 3a 3a 1a VFB ROM Consecutive 1 Random 1a VDB RAM Consecutive 1 1 1 1 1 Random 1...

Page 128: ...128 Chapter 3 CPU System Functions Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 129: ...l frequency of 240 KHz Features summary Special features of the clock generator are Choice of oscillators to reduce power consumption in stand by mode Frequency multiplication by two PLL synthesizers...

Page 130: ...programmable frequency multiplier divider that can multiply the frequency of the main oscillator by up to 16 The SSCG can supply the CPU system Standby PRS0 AFCAN UARTA CSIB TMZ TMP WCT SG Standby PCL...

Page 131: ...interface is supplied by the main oscillator or the PLL 3 Special clocks The figure shows also some special clock signals These are dedicated clocks for the LCD Controller Driver Watch Timer Watchdog...

Page 132: ...CLK must be enabled before it can be used WDTCLK This is the clock for the Watchdog Timer that is used for recovering from a system deadlock WDTCLK is available and hence the Watchdog Timer running as...

Page 133: ...enerator PLL SSCG frequency multipliers dividers Watch Timer and Watchdog Timer remain operating This mode allows quick return to the normal operating mode in response to a release signal because it i...

Page 134: ...perates CPU access to peripherals that have no clock supply may cause system deadlock Table 4 2 Clock Generator status after reset release Item Status Remarks Main oscillator stopped started by intern...

Page 135: ...e Electrical Target Specification 4 If the SSCG is going to be used Write SSCG registers to set up the SSCG This is only possible when the SSCG is switched off Start the SSCG set CKC SCEN and wait unt...

Page 136: ...ator clock monitor control register CLMCS FFFF F71AH Command protection register PHCMD FFFF F800H Peripheral status register PHS FFFF F802H Power save mode register PSM FFFF F820H Clock Generator cont...

Page 137: ...locks WCC Watchdog Timer clock control register on page 150 TCC Watch Timer clock control register on page 152 SCC SPCLK control register on page 154 FCC FOUTCLK control register on page 155 ICC IIC c...

Page 138: ...n setting PLLEN or SCEN to 1 Before selecting the SSCG PLL outputs as clock sources for peripherals ensure by software that the SSCG PLL stabilization time has elapsed The stabilization times are defi...

Page 139: ...de request This bit is set when the clock generator has completely set up it s power save mode configuration i e all registers are set up PLL and SSCG are switched off However if CGSTAT CMLPSM was alr...

Page 140: ...does not follow immediately all protected registers are write locked again Caution In case a high level programming language is used make sure that the compiler translates the two write instructions...

Page 141: ...d by any reset Note PHS PRERR is set if a write access to register PHCMD is not directly followed by a write access to one of the write protected registers 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PRERR Ra a The...

Page 142: ...the initial setting To ensure correct operation of the main oscillator the internal feed back resistor must remain connected 4 CLS Processor clock source monitor flag 0 Main oscillator operation sour...

Page 143: ...gister can be written only once after any reset The register is protected by a special sequence via the PHCMD register A fail of a write by the special sequence is reflected by PHS PRERR 1 If a write...

Page 144: ...The SSCG control registers SCFC0 SCFC1 and SCFMC can only be rewritten with new settings if the SSCG is switched off i e if the SSCG is disabled by CKC SCEN 0 the SSCG is safely switched off after a p...

Page 145: ...culation If dithering mode is disabled CKC DEN 0 the SSCG outputs it s center frequency fSSCGc fSSCGc 4 MHz x N M 2 where M m 1 SCFC0 SCFC0 2 0 1 N n 1 SCFC1 SCFC1 6 0 1 The values to be written into...

Page 146: ...register can be read written in 8 bit or 1 bit units Address FFFF F82EH Initial Value EBH The register is initialized by any reset Note 1 Bits 7 is set to 1 and must not be changed 2 This register ca...

Page 147: ...frequency fSSCG varies according to the FM range specified by SCFMC 4 2 around it s center value fSSCG fSSCGc FM range The time of one full cycle is given by the period of the modulation frequency sp...

Page 148: ...FC0 2BH SCFC1 DFH center frequency fSSCGc 48 MHz SCFMC 4 2 101B FM range 5 SCFMC 1 0 01B modulation frequency 50 kHz Then The SSCG frequency is swept between about 45 6 MHz and 50 4 MHz One sweep cycl...

Page 149: ...le bit CKC SCEN is cleared SSCG switched off 7 6 5 4 3 2 1 0 0 0a a These bits must not be altered 1a 0a 0 VBSPS2 VBSPS1 VBSPS0 R W R W R W R W R W R W R W R W Table 4 12 SCPS register contents Bit po...

Page 150: ...when certain power save modes are entered 1 WCC Watchdog Timer clock control register The 8 bit WCC register controls the Watchdog Timer clock This register can be changed only once after any reset Wr...

Page 151: ...me Function 7 SOSTP Sub oscillator STOP mode control 1 Sub oscillator will stop when STOP mode is entered 0 Sub oscillator will not stop when STOP mode is entered 6 to 4 WPS 2 0 WDT clock divider sele...

Page 152: ...PHCMD Command protection register on page 140 for details Address FFFF F836H Initial Value 00H The register is initialized at power on and by external RESET 7 6 5 4 3 2 1 0 0 WTPS2 WTPS1 WTPS0 0 WTSOS...

Page 153: ...ormed by the special sequence after the register has already once been written successfully PHS PRERR remains 0 though the write has been ignored PHS PRERR shows violations of the special sequence onl...

Page 154: ...ess FFFF F832H Initial Value 00H The register is initialized by entering WATCH Sub WATCH or STOP mode Note 1 Main osc is the clock provided by the main oscillator 2 PLL is the clock provided by the PL...

Page 155: ...ng the FOEN bit to minimize power consumption in stand by modes 2 There is an upper frequency limit for the output buffer of the FOUTCLK function Do not select a frequency higher than the maximum outp...

Page 156: ...ATCH Sub WATCH and STOP mode IICSEL1 is cleared the main oscillator is selected as the I2 C clock source Pay attention if PSM OSCDIS 1 before entering any of the above power save modes because the mai...

Page 157: ...t PSM register specifies the power save mode and controls the clock generation after reset and Sub WATCH mode release In addition it specifies the source of the Watch Calibration Timer clock WCTCLK Ac...

Page 158: ...lied with the selected sub clock either sub oscillator or ring oscillator see bit PCC SOSCP Since the reset value of OSCDIS is 1 and PCC SOSCP is 0 the CPU starts always with the ring oscillator clock...

Page 159: ...on refer to Power save mode activation on page 179 7 6 5 4 3 2 1 0 0 NMIWDT NMI0 INTM 0 0 STP 0 R R W R W R W R R R W R Table 4 19 PSC register contents Bit position Bit name Function 6 NMIWDT Mask fo...

Page 160: ...is inhibited Access This register can only be written in 8 bit units Address FFFF F1FCH Initial Value The contents of this register is undefined Caution Before writing to PRCMD make sure that all DMA...

Page 161: ...during the initialization If a dedicated microcontroller does not include any of the voltage regulators dedicated to the controls bit STBCTL STBYCD andSTBCTL STBYMD the status of the control bit has...

Page 162: ...ister the first write access to register STBCTL is valid All subsequent write accesses are ignored Thus the value of STBCTL can only be rewritten in a specified sequence and illegal write access is in...

Page 163: ...ting to this register is protected by a special sequence of instructions Please refer to PRCMDCMM CLMM write protection register on page 164 for details Address FFFF F870H Initial Value 00H This regis...

Page 164: ...specified sequence and illegal write access is inhibited Access This register can only be written in 8 bit units Address FFFF FCB0H Initial Value The contents of this register is undefined After writ...

Page 165: ...a has been written to the PRCMDCMS register the first write access to register CLMS is valid All subsequent write accesses are ignored Thus the value of CLMS can only be rewritten in a specified seque...

Page 166: ...te 1 The sub oscillator clock monitor can only be started if it has been enabled by setting CLMS CLMES to 1 2 Make sure that the sub oscillator stabilization time has elapsed before starting the clock...

Page 167: ...ing If the oscillator is switched off during stand by the associated clock monitor enters stand by as well Wake up signals The following signals can awake the controller from power save modes IDLE WAT...

Page 168: ...als the non maskable interrupts NMI0 NMIWDT all maskable interrupts To grant wake up capability to maskable interrupts these interrupts have to be unmasked by setting the dedicated mask flags xxMK to...

Page 169: ...lease all clock settings remain unchanged The CPU clock resumes operation Table 4 24 Clock Generator status in HALT mode Item Status Remarks Main oscillator unchanged Sub oscillator operates Ring osci...

Page 170: ...e it continues operating The IDLE mode can be released by the unmasked maskable interrupts INTPn INTCnWUP INTWTnUV INTTM01 INTVCn INTCBnR NMI0 NMIWDT RESET RESPOC RESWDT RESCMM RESCMS On IDLE mode rel...

Page 171: ...opped before entering the WATCH mode the oscillation stabilization time for the ring oscillator is ensured by hardware after WATCH mode release PLL and SSCG remain stopped after WATCH release Peripher...

Page 172: ...oscillator was stopped before entering the Sub WATCH mode the oscillation stabilization time for the ring oscillator is ensured by hardware after Sub WATCH release PLL and SSCG remain stopped after Su...

Page 173: ...enerator in the different states Normal describes all status except reset and power save modes The HALT mode is not listed in the table It does not change any of the table items but stoppes only the C...

Page 174: ...on stop on OSCDIS 1 stop stop n a stop n a stop Sub osc SOSTP 1 n a on on stop on on on SOSTP 0 on on Ring osc ROSTP 1 n a on on stop on stop on stop on ROSTP 0 on on on on SSCG PLL SSCG stby scen sce...

Page 175: ...1 n a MOCLK MOCLK MOCLK MOCLK MOCLK MOCLK MOCLK Watchdog Timer WDTCLK SOSC 0 WDTSEL0 0 WDTSEL1 0 off ROSCK ROSCK off ROSCK off ROSCK off ROSCK off ROSCK WDTSEL1 1 n a ROSCK ROSCK off b ROSCK off b RO...

Page 176: ...e these clocks are automatically changed to MOCLK b ROCLK SOCLK remains clock source but ring oscillator sub oscillator may be stopped in the respective power save mode by WCC ROSTP 1 WCC SOSTP 1 c MO...

Page 177: ...0 SBCLK ROCLK 1 SBCLK SOCLK MainOSC PCC write prohibited VBCLK MOCLK MainOSC PCC write permitted VBCLK MOCLK IDLE mode MainOSC unchanged off SubOSC on RingOSC on off Sub WATCH mode MainOSC on off SubO...

Page 178: ...se from Sub WATCH PSM 1 0 11B and OSCDIS 0 WATCH PSM 1 0 10B PSM entry with PSM 1 0 01B STOP PSM 1 0 11B Sub WATCH PSM 1 0 10B WATCH and OSCDIS 1 PSM release from Sub WATCH PSM 1 0 11B and OSCDIS 1 Ri...

Page 179: ...terrupts by IMRm xxMK 0 refer to IMR0 to IMR5 Interrupt mask registers on page 214 2 Mask all other interrupts i e none wake up capable interrupts wake up capable interrupts which shall not be used fo...

Page 180: ...ledged before the store to PSC This presupposes that both store instructions are performed consecutively as shown in the above example If another instruction is placed between steps 7 and 8 an interru...

Page 181: ...n The clock for the CPU system can be switched only once after reset or power save mode release The clocks for the Watchdog Timer Watch Timer and LCD Controller Driver can be switched only once after...

Page 182: ...cally started As a result the main oscillator is chosen and enabled as the source for the CPU system clock VBCLK After WATCH In WATCH mode the main oscillator operation depends on PSM OSCDIS If PSM OS...

Page 183: ...before entering Sub WATCH the main oscillator remains stopped and the CPU is clocked by a sub clock PCC CLS 1 PCC CKS 1 0 xxB Sub clock means the clocks supplied by either the 32 KHz sub oscillator or...

Page 184: ...sed before the WCT can operate 4 4 3 Clock output FOUTCLK The Clock Generator output signal FOUTCLK supplies a clock for external components It can be derived from any internal clock source that means...

Page 185: ...of the sub oscillator it generates the reset request RESCMS 2 Start and stop Before the clock monitors can be started they have to be enabled by setting CLMM CLMEM and CLMS CLMES to 1 Main oscillator...

Page 186: ...ub oscillator clock monitor is sometimes already started by setting CLMS CLMES 1 i e without CLMCS CMRT 1 In these cases it would not be required to start the sub oscillator by setting CLMCS CMRT 1 ad...

Page 187: ...ogrammable priorities can be specified for each interrupt request Starting of interrupt servicing takes no fewer than 5 system clocks after the generation of an interrupt request 5 1 Features Interrup...

Page 188: ...nterrupt 0 PORT 6 00E0H 000000E0H next PC Interrupt INTP1 External interrupt 1 PORT 7 00F0H 000000F0H next PC Interrupt INTP2 External interrupt 2 PORT 8 0100H 00000100H next PC Interrupt INTP3 Extern...

Page 189: ...0 TMG1 39 02F0H 000002F0H next PC Interrupt INTTG1OV1 TMG1 overflow interrupt 1 TMG1 40 0300H 00000300H next PC Interrupt INTTG1CC0 TMG1 capture compare channel 0 TMG1 41 0310H 00000310H next PC Inte...

Page 190: ...ed Reserved 65 0490H 00000490H next PC Interrupt INTDMA0 DMA0 transmission end DMA0 66 04A0H 000004A0H next PC Interrupt INTDMA1 DMA1 transmission end DMA1 67 04B0H 000004B0H next PC Interrupt INTDMA2...

Page 191: ...00005F0H next PC Interrupt INTTG2CC5 TMG2 capture compare channel 5 TMG2 88 0600H 00000600H next PC Interrupt INTCB1RE CSIB1 receive error interrupt CSIB1 89 0610H 00000610H next PC Interrupt INTCB1R...

Page 192: ...rrupt 0 PORT 6 00E0H 000000E0H next PC Interrupt INTP1 External interrupt 1 PORT 7 00F0H 000000F0H next PC Interrupt INTP2 External interrupt 2 PORT 8 0100H 00000100H next PC Interrupt INTP3 External...

Page 193: ...upt 0 TMG1 39 02F0H 000002F0H next PC Interrupt INTTG1OV1 TMG1 overflow interrupt 1 TMG1 40 0300H 00000300H next PC Interrupt INTTG1CC0 TMG1 capture compare channel 0 TMG1 41 0310H 00000310H next PC I...

Page 194: ...PC Interrupt INTDMA1 DMA1 transmission end DMA1 67 04B0H 000004B0H next PC Interrupt INTDMA2 DMA2 transmission end DMA2 68 04C0H 000004C0H next PC Interrupt INTDMA3 DMA3 transmission end DMA3 69 04D0H...

Page 195: ...0H next PC Interrupt INTCB1RE CSIB1 receive error interrupt CSIB1 89 0610H 00000610H next PC Interrupt INTCB1R CSIB1 receive complete interrupt CSIB1 90 0620H 00000620H next PC Interrupt INTCB1T CSIB1...

Page 196: ...ception processing is started However the value of the PC saved when an interrupt is acknowledged during division DIV DIVH DIVU DIVHU instruction execution is the value of the PC of the current instru...

Page 197: ...If a NMI0 is generated while NMI0 is being serviced The new NMI0 request is held pending regardless of the value of the PSW NP bit The pending NMIVC request is acknowledged after servicing of the curr...

Page 198: ...maskable interrupt request acknowledgement operation multiple NMI requests generated at the same time NMI0 and NMIWDT requests generated simultaneously NMI0 and NMIWDT requests generated simultaneous...

Page 199: ...NP 0 set before NMIWDT request NMIWDT NMI0 request generated during NMIWDT servicing NMI1 request generated during NMIWDT servicing Main routine NMI0 request NMI0 request NMI0 servicing Held pending...

Page 200: ...bits of the PSW and clears the EP bit 5 Sets the handler address corresponding to the non maskable interrupt to the PC and transfers control The processing configuration of a non maskable interrupt is...

Page 201: ...5 4 illustrates how the RETI instruction is processed Figure 5 4 RETI instruction processing Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during non maskable interrup...

Page 202: ...ged 5 2 4 NMI0 control The NMI0 can be configured to generate an NMI upon a rising falling or both edges at the NMI pin To enable respectively disable the NMI0 and to configure the edge refer to Edge...

Page 203: ...ss specified by the interrupt control register Note that only interrupts with a higher priority will have this capability interrupts with the same priority level cannot be nested However if multiple i...

Page 204: ...set by the RETI and LDSR instructions input of the pending INT starts the new maskable interrupt processing INT input xxIF 1 No xxMK 0 No Is the interrupt mask released Yes Yes No No No Maskable inter...

Page 205: ...rocessing of the RETI instruction Figure 5 6 RETI instruction processing Note 1 For the ISPR register see ISPR In service priority register on page 216 2 The solid lines show the CPU processing flow C...

Page 206: ...interrupts having the same priority level specified by the xxPRn bit are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt reques...

Page 207: ...cessing of c Interrupt request c level 3 Processing of d Processing of e EI Interrupt request e level 2 Processing of f EI Processing of g Interrupt request g level 1 Interrupt request h level 1 Proce...

Page 208: ...r level 0 Interrupt request u level 2 Note 2 Interrupt request t level 2 Note 1 Processing of p Processing of q Processing of r EI If levels 3 to 0 are acknowledged Interrupt request j is held pendin...

Page 209: ...le interrupts When returning from multiple interrupt servicing restore the values of EIPC and EIPSW after executing the DI instruction Remark a to c in the figure are the temporary names of interrupt...

Page 210: ...LCD The address and bit of each interrupt control register are shown in the following table 7 6 5 4 3 2 1 0 Address Initial value xxIC xxIF xxMK 0 0 0 xxPR2 xxPR1 xxPR0 FFFF F110H to FFFF F18EH 47H Bi...

Page 211: ...0 0 TP0CC0PR2 TP0CC0PR1 TP0CC0PR0 FFFFF13AH TP0CC1IC TP0CC1IF TP0CC1MK 0 0 0 TP0CC1PR2 TP0CC1PR1 TP0CC1PR0 FFFFF13CH TP1OVIC TP1OVIF TP1OVMK 0 0 0 TP1OVPR2 TP1OVPR1 TP1OVPR0 FFFFF13EH TP1CC0IC TP1CC0...

Page 212: ...RPR0 FFFFF18CH UA1TIC UA1TIF UA1TMK 0 0 0 UA1TPR2 UA1TPR1 UA1TPR0 FFFFF18EH IIC0IC IIC0IF IIC0MK 0 0 0 IIC0PR2 IIC0PR1 IIC0PR0 FFFFF190H IIC1IC IIC1IF IIC1MK 0 0 0 IIC1PR2 IIC1PR1 IIC1PR0 FFFFF194H DM...

Page 213: ...FFFFF1C2H CB1REIC CB1REIF CB1REMK 0 0 0 CB1REPR2 CB1REPR1 CB1REPR0 FFFFF1C4H CB1RIC CB1RIF CB1RMK 0 0 0 CB1RPR2 CB1RPR1 CB1RPR0 FFFFF1C6H CB1TIC CB1TIF CB1TMK 0 0 0 CB1TPR2 CB1TPR1 CB1TPR0 FFFFF1C8H...

Page 214: ...11 10 9 8 Address Initial value IMR0 TZ2UVMK TZ1UVMK TZ0UVMK P6MK P5MK P4MK P3MK P2MK FFFFF100H FFFFH 7 6 5 4 3 2 1 0 P1MK P0MK 1 TM00MK WT1UVMK WT0UVMK VC1MK VC0MK 15 14 13 12 11 10 9 8 Address Init...

Page 215: ...108H FFFFH 7 6 5 4 3 2 1 0 INT71MK INT70MK DMA3MK DMA2MK DMA1MK DMA0MK SG0MK IIC1MK 15 14 13 12 11 10 9 8 Address Initial value IMR5 LCDMK 1 1 1 CB1TMK CB1RMK CB1REMK TG2CC5MK FFFFF10AH FFFFH 7 6 5 4...

Page 216: ...PR ISPR7 ISPR6 ISPR5 ISPR4 ISPR3 ISPR2 ISPR1 ISPR0 FFFFF19AH 00H Bit position Bit name Function 7 to 0 ISPR7 to ISPR0 Indicates priority of interrupt currently acknowledged 0 Interrupt request with pr...

Page 217: ...stand by mode of INTPn upon Rising edge Falling edge Both edges rising and falling edge For configuration of the external interrupt events refer to Edge and Level Detection Configuration on page 218...

Page 218: ...00 FFFF F700H 00H R W R R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Address Initial value INTM1 0 ELSEL3 ESEL31 ESEL30 0 ELSEL2 ESEL21 ESEL20 FFFF F702H 00H R W R R W R W R W R R...

Page 219: ...annot be disabled by software Specify INTM0 ESEL0 1 0 before or at the same time with setting INTM0 NMIEN 1 Note that INTM0 ESEL0 can be written independently of INTM0 NMIEN NMIEN ESEL0 ESEL01 ESEL00...

Page 220: ...ID bits of the PSW 5 Sets the handler address 00000040H or 00000050H corresponding to the software exception to the PC and transfers control Figure 5 10 illustrates the processing of a software excep...

Page 221: ...C and PSW Figure 5 11 illustrates the processing of the RETI instruction Figure 5 11 RETI instruction processing Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction duri...

Page 222: ...ted when an instruction applicable to this illegal instruction is executed Note Arbitrary 1 Operation If an exception trap occurs the CPU performs the following processing and transfers control to the...

Page 223: ...estored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Figure 5 13 illustrates the restore processing from an exception...

Page 224: ...wing processing transfers control to the debug monitor routine and shifts to debug mode 1 Saves the restored PC to DBPC 2 Saves the current PSW to DBPSW 3 Sets the NP EP and ID bits of the PSW 4 Sets...

Page 225: ...during processing if there is an interrupt request with a higher priority level and the higher priority interrupt request is received and processed first If there is an interrupt request with a lower...

Page 226: ...ister EIPSW saved to memory or register EI instruction interrupt acknowledgment enabled Higher priority maskable interrupt acknowledgment DI instruction interrupt acknowledgment disabled Saved value r...

Page 227: ...control is resumed after the processing of the higher priority interrupt has been completed and the RETI instruction has been executed A pending interrupt request is acknowledged after the current int...

Page 228: ...e interrupt request non sampling instructions are as follows EI instruction DI instruction LDSR reg2 0x5 instruction for PSW The store instruction for the interrupt control register PlCn in service pr...

Page 229: ...adjustment when starting mass production 6 1 Overview Features summary Internal VFB flash memory PD70F3427 PD70F3426 PD70F3425 1 MB PD70F3424 PD70F3423 512 KB PD70F3422 384 KB PD70F3421 256 KB PD70F3...

Page 230: ...y blocks The PD70F3424 PD70F3423 512 KB flash memory is made up of 128 blocks Figure 6 2 shows the address assignment of the flash memory blocks Figure 6 2 Address assignment of PD70F3424 PD70F3423 fl...

Page 231: ...6 KB flash memory is made up of 64 blocks Figure 6 4 shows the address assignment of the flash memory blocks Figure 6 4 Address assignment of PD70F3421 flash memory blocks 0006 0000H 0005 F000H 0005 E...

Page 232: ...es All blocks batch erasure Following areas can be erased all together PD70F3427 PD70F3426 PD70F3425 0000 0000H to 000F FFFFH PD70F3424 PD70F3423 0000 0000H to 0007 FFFFH PD70F3422 0000 0000H to 0005...

Page 233: ...iately after release of a system reset Refer to Operation Modes on page 114 for details on how to enter normal operation or external flash programming mode 6 1 4 Boot block swapping The microcontrolle...

Page 234: ...ser mode of the microcontroller Self programming must be in particular enabled in order to avoid unintended re programming of the flash Two ways to enable self programming are provided by setting the...

Page 235: ...NP register the first write access to register SELFEN is valid All subsequent write accesses are ignored Thus the value of SELFEN can only be rewritten in a specified sequence and illegal write access...

Page 236: ...l memory by use of the SelfLib_UsrIntToRam self programming library function The addresses of the interrupt handler routines are set up via the SelfLib_RegisterInt self programming library function No...

Page 237: ...amming of the flash memory can be performed by the debug tool running on the host machine Caution Programming the flash memory during debug sessions by the debug tool adds to the performed number of w...

Page 238: ...before the device is mounted on the target system by using a dedicated program adapter FA series All signals including clock and power supply are provided by the external flash programmer Note The FA...

Page 239: ...and the microcontroller utilizes the Asynchronous Serial Interface UARTA0 or optionally the synchronous serial interface CSIB0 For programming via the synchronous serial interface CSIB0 without hands...

Page 240: ...nals for the microcontroller For details refer to the PG FP4 User s Manual U15260E flash programmer FLMD0 FLMD1Note VDD VSS RESET SOB0 SIB0 SCKB0 FLMD0 FLMD1Note VDD GND RESET SI SO SCK PG FP4 Flash P...

Page 241: ...HS FLMD0 Output Write enable disable mode setting FLMD0 FLMD1 Output Mode setting FLMD1 VDD I O VDD voltage generation voltage monitor VDD GND Ground VSS CLK Output Clock output to the controller X1...

Page 242: ...tor at the FLMD0 pin ensures normal operation mode if no flash programmer is connected In the flash memory programming mode the VDD write voltage is supplied to the FLMD0 pin Additionally the FLMD1 pi...

Page 243: ...lated or set in high impedance state Ensure that the other devices do not malfunction because of flash programmer signals 3 Pay attention in particular if the flash programmer s RESET signal is connec...

Page 244: ...sh programmer set the microcontroller in the flash memory programming mode To set this mode set the FLMD0 and FLMD1 pins as shown in Table 6 3 and release RESET The communication interface is chosen b...

Page 245: ...able below Note When UARTA0 is selected the receive clock is calculated based on the reset command that is sent from the flash programmer after reception of the MODE pulses VDD FLMD1 input FLMD0 input...

Page 246: ...S UARTA Blank check Block blank check command Checks erasure status of entire memory Erase Chip erase command Erase all memory contens including area that holds security flags reset vector and other f...

Page 247: ...ommand to the command issued by the flash programmer The response commands sent by the microcontroller are listed below Table 6 7 Response commands Response command name Function ACK Acknowledges comm...

Page 248: ...248 Chapter 6 FlashMemory Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 249: ...t of chip select area k 7 1 Overview The following external devices can be connected to the microcontroller device SRAM RAM ROM External I O Features summary The bus and memory control of the microcon...

Page 250: ...ram of the modules that are necessary for accessing on chip peripherals external memory or external I O Figure 7 1 Bus and Memory Control diagram Busses The busses are abbreviated as follows NPB NEC p...

Page 251: ...bytes of the 32 bit data bus D 31 0 The Memory Controller generates the control signals for access to the external devices For example it generates the read strobe RD and the write strobe WR From the...

Page 252: ...ternal access access to that memory bank generates the corresponding chip select signal see Figure 7 3 on page 254 The combination of memory banks that activate the same chip select signal is called c...

Page 253: ...2 MB Bank 12 2 MB Bank 8 8 MB Bank 9 8 MB Bank 10 4 MB Bank 11 4 MB 0000 0000H 0020 0000H 0000 0000H 000F FFFFH 0010 0000H 001F FFFFH 0040 0000H 0060 0000H 0060 5FFFH 0060 0000H 0080 0000H 00C0 0000H...

Page 254: ...0 0000H 0080 0000H 0080 0000H 007F FFFFH 00C0 0000H 0100 0000H 0100 0000H 00FF FFFFH 0180 0000H 0200 0000H 0200 0000H 01FF FFFFH 0280 0000H 0300 0000H 0300 0000H 02FF FFFFH 0340 0000H 0380 0000H 0380...

Page 255: ...generated If during access to bank 2 CS2 should not be active activate CS0 for this bank CSC0 CS02 1 Due to the priority order only chip select signal CS0 will be active for bank 2 7 2 3 Peripheral I...

Page 256: ...rea overlaps one of the following areas the programmable peripheral I O area becomes ineffective Peripheral I O area ROM area RAM area Note 1 The fixed peripheral I O area is mirrored to the upper 4 K...

Page 257: ...ccesses to NPB peripheral I O registers via the programmable peripheral I O area Since the CPU may continue operation even though the data has not yet been transferred to its destination register inco...

Page 258: ...he data format that means address 4n for words address 2n for halfwords Unaligned halfword data access When the LSB of the address is A0 1 two byte accesses are performed Unaligned word data access Wh...

Page 259: ...the starting bus cycle 5 Bus cycle control register BCC Set the number of idle states for each chip select area 6 Page ROM configuration register PRC If page ROM mode is selected BCTn BTk0 1 set wheth...

Page 260: ...nternal peripheral function wait control register VSWC FFFF F06EH Chip area select control registers CSC0 FFFF F060H CSC1 FFFF F062H Endian configuration register BEC FFFF F068H PD70F3427 only Memory...

Page 261: ...sets the start address of the 16 KB PPA in a range of 256 MB The 256 MB page is mirrored 16 times to the entire 32 bit address range The base address PBA is calculated by PBA BPC PA 13 0 x 214 Table 7...

Page 262: ...ation the programmable peripheral area is mapped to the address range 03FE C000H to 03FE FFFFH With this setting the CAN message buffer registers are accessible via the addresses given in CAN Controll...

Page 263: ...egister contents Bit position Bit name Function 6 to 4 SUWL 2 0 Address setup wait for internal bus SUWL2 SUWL1 SUWL0 Number of address setup wait states 0 0 0 0 0 0 1 1 CPU system clock VBCLK 0 1 0 2...

Page 264: ...mmended timing for internal bus System clocka fVBCLK a When deriving the system clock from the modulated clock of the SSCG the maximum clock deter mines the correct register setting 16 MHz 25 MHz 33 M...

Page 265: ...FF F060H CSC1 FFFF F062H Initial Value 2C11H Thess registers must be initialized as described in Table 7 13 and Table 7 14 The register contents in Table 7 11 and Table 7 12 read as follows CSkm 0 Cor...

Page 266: ...1 1 8 CS20 0 7 CS13 5 CS1 6 CS12 4 5 CS11 2 or 3 0 CS10 0 or 1 3 CS03 3 CS0 2 CS02 2 1 CS01 1 0 CS00 0 Table 7 12 CSC1 register contents Bit Position Bit Name Access to memory bank Chip select signal...

Page 267: ...FFFFH CSC0 CS0 3 0 must be left with their default value 1000B CSC0 CS1 3 0 1000B CSC0 CS1 3 0 must be left with their default value 1000B CSC0 CS2 3 0 1000B CS2 assigned to bank 3 to VSB RAM memory 0...

Page 268: ...ault value is 1 CSC0 CS2 3 0 1100B CSC0 CS2 3 0 must be left with their default value 1100B CSC0 CS3 3 0 xxx0B Set CSC0 CS3 3 1 as required to assign CS3 to bank 4 to 7 to external memory 080 0000H 1F...

Page 269: ...gister after initialization Do not access external devices before initialization is finished Note 1 Accesses to all internal resources are fixed to little endian format 2 Different chip select signals...

Page 270: ...with their default value 0 BEC BE30 0B BEC BE30 must be left with their default value 0 BEC BE40 0B BEC BE40 must be left with their default value 0 BEC BE50 0B BEC BE50 must be left with their defaul...

Page 271: ...Initial Value 4444H Caution 1 The bits marked with 0 must always be 0 2 The bits marked with 1 must always be 1 3 To initialize an external memory area after a reset registers BCTn have to be set Do...

Page 272: ...t units Address FFFF F48EH Initial Value AAAAH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LB71 LB70 LB61 LB60 LB51 LB50 LB41 LB40 LB31 LB30 LB21 LB20 LB11 LB10 LB01 LB00 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Tab...

Page 273: ...t function WAIT pin is disabled 2 For access to internal memory the setting of register ASC is neglected No wait states are inserted after address setup Caution To initialize an external memory area a...

Page 274: ...PRC register setting Caution To initialize an external memory area after a reset this register has to be set Do not access external devices before initialization is finished Do not change this registe...

Page 275: ...For access to internal memory no idle states are inserted Caution To initialize an external memory area after a reset this register has to be set Do not access external devices before initialization...

Page 276: ...and 1 bit units Address FFFF FF00H Initial Value 00H Caution To initialize an external memory area after a reset this register has to be set Do not access external devices before initialization is fi...

Page 277: ...Bit name Function 14 to 12 PRW 2 0 Page ROM on page wait control Sets the number of data waits corresponding to the internal system clock PRW 2 0 Inserted data wait states 000B No wait state inserted...

Page 278: ...o not change this register after initialization Do not access external page ROM devices before initialization is finished Caution To initialize an external memory area after a reset this register has...

Page 279: ...nected page ROM and the number of continuously readable bits Wait control for normal access off page and page access on page is specified by different registers For page access wait control is perform...

Page 280: ...16 bit 3 32 bit data bus width The page size or the number of continuously readable bits is 2 x 32 bit To provide 2 addresses a 1 bit on page address is required Therefore set PRC MA 6 3 0000B Note F...

Page 281: ...ize 2 x 32 bit A4 A0 Internal address latch immediately preceding address Output address Page ROM address Off page address MA6 0 MA5 0 MA4 0 MA3 0 PRC register setting Comparison A3 A5 A6 A7 A22 A4 A3...

Page 282: ...e low order byte of the word is stored in memory at the lowest address and the high order byte at the highest address Therefore the base address of the word addresses the low order byte Figure 7 9 Lit...

Page 283: ...cle for accessing slow external devices any number of wait states TW can be inserted under external control of the WAIT signal The WAIT signal can be set asynchronously from the system clock The WAIT...

Page 284: ...T2 state when accessing SRAM external I O external ROM or page ROM The number of idle states can be specified by program using the bus cycle control register BCC 7 6 External Devices Interface Timing...

Page 285: ...B no address setup wait states inserted DWCm DWk 2 0 000B no programmable data wait states inserted BCC BCk 1 0 00B no idle states inserted Note 1 The circles indicate the sampling timing 2 The broken...

Page 286: ...ess setup wait state inserted DWCm DWk 2 0 000B no programmable data wait states inserted BCC BCk 1 0 01B one idle state inserted Note 1 The circles indicate the sampling timing 2 The broken line indi...

Page 287: ...ected external device is SRAM or external I O ASC ACk 1 0 00B no address setup wait states inserted DWCm DWk 2 0 000B no programmable data wait states inserted BCC BCk 1 0 00B no idle states inserted...

Page 288: ...al device is SRAM or external I O ASC ACk 1 0 01B one address setup wait state inserted DWCm DWk 2 0 000B no programmable data wait states inserted BCC BCk 1 0 01B one idle state inserted Note 1 The c...

Page 289: ...DWCm DWk 2 0 000B no programmable data wait states inserted BCC BCk 1 0 00B no idle states inserted Note 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance stat...

Page 290: ...DWCm DWk 2 0 000B no programmable data wait states inserted BCC BCk 1 0 00B no idle states inserted Note 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state...

Page 291: ...e that is inserted according to the DWC0 and DWC1 register settings and according to the WAIT input TOW state Wait state that is inserted according to the PRC PRW 2 0 settings and according to the WAI...

Page 292: ...k 1 0 00B no address setup wait states inserted DWCm DWk 2 0 010B two programmable data wait states for off page access inserted PRC PRW 2 0 001B one programmable data wait state for on page access in...

Page 293: ...state inserted DWCm DWk 2 0 000B no programmable data wait states for off page access inserted PRC PRW 2 0 000B no programmable data wait states for on page access inserted BCC BCk 1 0 see Figure 7 18...

Page 294: ...k 1 0 00B no address setup wait states inserted DWCm DWk 2 0 010B two programmable data wait states for off page access inserted PRC PRW 2 0 001B one programmable data wait state for on page access in...

Page 295: ...state inserted DWCm DWk 2 0 000B no programmable data wait states for off page access inserted PRC PRW 2 0 000B no programmable data wait states for on page access inserted BCC BCk 1 0 see Figure 7 20...

Page 296: ...ess 8 bits a Little endian Figure 7 21 Left Access to even address 2n Right Access to odd address 2n 1 b Big endian Figure 7 22 Left Access to even address 2n Right Access to odd address 2n 1 7 0 7 0...

Page 297: ...Halfword data 15 8 External data bus 2n 1 Address 2n 1 st Access 2 nd Access 1 st Access 2 nd Access 7 0 7 0 Halfword data 15 8 External data bus Address 7 0 7 0 Halfword data 15 8 External data bus 2...

Page 298: ...ta External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus...

Page 299: ...bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 5 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus Address 15 8 4n...

Page 300: ...l data bus 4n 1 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus Address 15...

Page 301: ...bus 4n 3 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus Address 15 8 4n...

Page 302: ...1 Byte access 8 bits a Little endian Figure 7 33 Left Access to even address 2n Right Access odd address 2n 1 b Big endian Figure 7 34 Left Access to even address 2n Right Access to odd address 2n 1...

Page 303: ...1 st Access 2 nd Access 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 2 Address 7 0 7 0 Halfword data 15 8 External data bus 2n A...

Page 304: ...ess 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 2 Address 15 8 4n 3 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 1 23 16 31 24 7 0...

Page 305: ...16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 4n 5 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15...

Page 306: ...n 2 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 1 Address 15 8 4n 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word da...

Page 307: ...16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 3 Address 15 8 4n 2 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15...

Page 308: ...308 Chapter 7 Bus and Memory Control BCU MEMC Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 309: ...ts 8 16 and 32 bits Maximum transfer count 65536 216 Two transfer modes independently selectable for each DMA channel Single transfer mode Block transfer mode Transfer requests Requests by dedicated p...

Page 310: ...LK0 PLL 2 16 24 00 SCC 03H SCPS SPSPS 2 0 001B SSCG 32 MHz SPCLK0 fSSCGPS 16 24 00 SCC 03H SCPS SPSPS 2 0 011B SSCG 48 MHz SPCLK0 fSSCGPS 12 18 00 UARTA CKC PERIC 0 PCLK1 MainOsc 4 6 00 CKC PERIC 1 PL...

Page 311: ...sc 4 6 00 SPCLK5 MainOsc 0 5 0 75 SCC 01H SPCLK0 PLL 2 16 24 00 SPCLK1 PLL 4 8 12 00 SPCLK2 MainOsc 4 6 00 SPCLK5 MainOsc 0 5 0 75 SCC 03H SCPS SPSPS 2 0 001B SSCG 32 MHz SPCLK0 fSSCGPS 16 24 00 SPCLK...

Page 312: ...Initial value DSAH0 IR 0 0 0 SA26 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 FFFFF082H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAH1 IR 0 0 0 SA26 SA26 SA25 SA24...

Page 313: ...A13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF088H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAL2 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 S...

Page 314: ...value DDAH0 IR 0 0 0 DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 FFFFF086H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAH1 IR 0 0 0 DA27 DA26 DA25 DA24 DA23 DA...

Page 315: ...3 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF08CH undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAL2 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2...

Page 316: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DBC0 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 B2C BC1 BC0 FFFFF0C0H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address In...

Page 317: ...FF0D4H 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DADC3 DS1 DS0 0 0 0 0 0 0 SAD1 SAD0 DAD1 DAD0 TM1 TM0 0 0 FFFFF0D6H 0000H Bit position Bit name Function 15 14 DS1 DS0 Sets the...

Page 318: ...nnot be accessed during DMA operation 3 2 TM1 TM0 Sets the transfer mode during DMA transfer TM1 TM0 Transfer mode 0 0 Single transfer mode 0 1 Setting prohibited 1 0 Setting prohibited 1 1 Block tran...

Page 319: ...i Link Enable bit MLE is set to 1 at terminal count output the ENn bit is not cleared to 0 and the DMA transfer enable state is retained refer to Automatic Restart Function on page 323 Moreover the ne...

Page 320: ...4 3 2 1 0 Address Initial value DRST 0 0 0 0 EN3 EN2 EN1 EN0 FFFFF0F2H 00H Bit position Bit name Function 3 to 0 EN3 to EN0 Specifies whether DMA transfer through DMA channel n is to be enabled or di...

Page 321: ...according to the following table Caution If the DMA trigger source is changed by modifying DTFRn IFCn 2 0 bits while DMA channel n is active a DMA request may be set accidentally Proceed in any of th...

Page 322: ...rigger sources In case of a receive overflow or a framing or parity error condition no DMA trigger will be issued The receive error interrupt INTUAnRE of the respective UARTn should be enabled to info...

Page 323: ...wever the DMA transfer end interrupt is issued even if DMA transfer is automatically started This mode is called multi link mode and is configured by DCHCn MLEn 1 If DMA channel n is disabled DCHCn EN...

Page 324: ...e source address is output and reading is performed from the source to the DMAC In the second cycle the transfer destination address is output and writing is performed from the DMAC to the transfer de...

Page 325: ...m the on chip peripheral I O that is set in the DTFRn register the DMA transfer starts ENn bit 1 TCn bit 0 2 Request from software If the STGn the ENn and the TCn bits of the DCHCn register are set as...

Page 326: ...r of channel 3 which begins during the DMA block transfer of DMA channel 2 The block transfer of DMA channel 2 is forcibly terminated by setting the INIT2 bit of its DCHC2 control register Figure 8 3...

Page 327: ...isters the next transfer condition can be set even during a DMA transfer However a setting in the DADCn register is ignored refer to Automatic Restart Function on page 323 8 11 DMA Transfer Completion...

Page 328: ...r request is generated within one clock after the end of a single transfer even if the previous higher priority DMA transfer request signal stays active this request is not prioritized and the next DM...

Page 329: ...le When two DMA transfer request signals are activated at the same time the two DMA transfers are performed alternately Figure 8 7 Single transfer example 3 Note The bus is always released DMA Transfe...

Page 330: ...acknowledged during block transfer After the block transfer ends and the DMAC releases the bus and another DMA transfer can be acknowledged Figure 8 9 shows a block transfer mode example It is a block...

Page 331: ...ctions may conflict with the internal firmware 9 1 Overview The ROM Correction Function is used to replace part of the internal ROM or flash memory with user defined data By using this function progra...

Page 332: ...processing upon correction address match Enable Disable of each channel individually by software Caution The DBTRAP ROM correction unit is also used by the N Wire on chip debug unit Thus ROM correctio...

Page 333: ...the DBPC register which holds the address next to the correction address of CORADm which has caused the DBTRAP exception If non of CORADm matches DBPC 2 DBTRAP was generated by an illegal opcode detec...

Page 334: ...tion routine Branch to correction code address of corresponding channel m Execute fetch code Read data for setting ROM correction from external Execute DBTRAP instruction Jump to address 0000 0060H Ex...

Page 335: ...rrection of each channel Access This register can be read written in 8 and 1 bit units Address FFFF F9D0H Initial Value 0000H Note ROM correction of channel n should only be enabled after the correcti...

Page 336: ...FF F858H CORAD6H FFFF F85AH CORAD7 CORAD7L FFFF F85CH CORAD7H FFFF F85EH Initial Value 0000 0000H Caution The ROM correction address CORADm 19 0 must not exceed the upper address of the internal ROM r...

Page 337: ...OR2AD4H FFFF F8B2H COR2AD5 COR2AD5L FFFF F8B4H COR2AD5H FFFF F8B6H COR2AD6 COR2AD6L FFFF F8B8H COR2AD6H FFFF F8BAH COR2AD7 COR2AD7L FFFF F8BCH COR2AD7H FFFF F8BEH Initial Value 0000 0000H Caution The...

Page 338: ...ter 9 ROM Correction Function ROMC Siemens VDO Preliminary User s Manual U17566EE1V2UM00 S i e m e n s V D O s p e c i f i c J C P d o c u m e n t Downloaded from Elcodis com electronic components dis...

Page 339: ...N Wire debug interface For protection of the flash memory the usage of the debug interface can be protected and it can be disabled The debug interface is protected via a 10 byte ID code and an interna...

Page 340: ...e details refer to Security function on page 879 Table 10 1 Possible results of ID code comparison N Wire use enable flag ID code Protection Level 0 Xa a Codes are not compared Level 2 Full protection...

Page 341: ...n Set this flag to disable the chip erase function via flash writer interface This flag does not affect the self programming interface 3 Block erase protection flag Block erase protection function Set...

Page 342: ...342 Chapter 10 Code Protection and Security Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 343: ...f Timer P are identified by n for example TMPn or TPnCTL0 for the TMPn control register 0 11 1 Overview An outline of TMPn is shown below Clock selection 8 ways Capture trigger input pins 2 External e...

Page 344: ...topped when a breakpoint is hit during debugging refer to On Chip Debug Unit on page 877 11 3 Configuration TMPn includes the following hardware Figure 11 1 Block diagram of TMPn PCLK0 16 MHz PCLK01 P...

Page 345: ...value of the 16 bit counter matches the value of the CCR0 buffer register a compare match interrupt request signal INTTPnCC0 is generated The CCR0 buffer register cannot be read or written directly T...

Page 346: ...tcut Address TMPn control registers 0 TPnCTL0 base TMPn control registers 1 TPnCTL1 base 1H TMPn I O control register 0 TPnIOC0 base 2H TMPn I O control register 1 TPnIOC1 base 3H TMPn I O control reg...

Page 347: ...t simultaneously 3 Be sure to clear bits 3 to 6 to 0 Note For information about PCLKx please refer to Clock Generator on page 129 7 6 5 4 3 2 1 0 TPnCE 0 0 0 0 TPnCKS2 TPnCKS1 TPnCKS0 R W R W R W R W...

Page 348: ...valid signal for external trigger input In one shot pulse output mode A one shot pulse is output with writing 1 to the TPnEST bit as the trigger In external trigger pulse output mode A PWM waveform is...

Page 349: ...performed clear the TPnCE bit to 0 and then set the bits again 2 Even if the TPnOLm bit is manipulated when the TPnCE and TPnOEm bits are 0 the TOPnm pin output level varies m 0 1 7 6 5 4 3 2 1 0 0 0...

Page 350: ...the free running timer mode and the pulse width measurement mode In all other modes a capture operation is not possible 7 6 5 4 3 2 1 0 0 0 0 0 TPnIS3 TPnIS2 TPnIS1 TPnIS0 R W R W R W R W R W R W R W...

Page 351: ...ts are valid only when the TPnCTL1 TPnEEE bit 1 or when the external event count mode TPnCTL1 TPnMD2 to TPnCTL1 TPnMD0 bits 001 has been set 7 6 5 4 3 2 1 0 0 0 0 0 TPnEES1 TPnEES0 TPnETS1 TPnETS0 R W...

Page 352: ...ster selected The TPnCCS1 bit setting is valid only in the free running timer mode 4 TPnCCS0 TPnCCR0 register capture compare selection 0 compare register selected 1 capture register selected The TPnC...

Page 353: ...itial Value 0000H This register is initialized by any reset a Function as compare register The TPnCCR0 register can be rewritten even when the TPnCTL0 TPnCE bit 1 The set value of the TPnCCR0 register...

Page 354: ...d reading the TPnCCR0 register conflict the correct value of the TPnCCR0 register can be read The following table shows the functions of the capture compare register in each mode and how to write data...

Page 355: ...mpare register The TPnCCR1 register can be read or written during operation Access This register can be read written in 16 bit units Address base 8H Initial Value 0000H This register is initialized by...

Page 356: ...d reading the TPnCCR1 register conflict the correct value of the TPnCCR1 register can be read The following table shows the functions of the capture compare register in each mode and how to write data...

Page 357: ...of the 16 bit timer can be read The value of the TPnCNT register is cleared to 0000H when the TPnCE bit 0 If the TPnCNT register is read at this time the value of the 16 bit counter FFFFH is not read...

Page 358: ...be output from the TOPn0 pin Usually the TPnCCR1 register is not used in the interval timer mode Figure 11 2 Configuration of interval timer Operation TPnCTL1 TPnESTBit Software Trigger Bit TIPn0 Pin...

Page 359: ...alue of the CCR0 buffer register the 16 bit counter is cleared to 0000H the output of the TOPn0 pin is inverted and a compare match interrupt request signal INTTPnCC0 is generated The interval can be...

Page 360: ...est signal INTTPnCC1 is generated when the count value of the 16 bit counter matches the value of the CCR1 buffer register Therefore mask the interrupt request by using the corresponding interrupt mas...

Page 361: ...0 Register initial setting TPnCTL0 register TPnCKS0 to TPnCKS2 bits TPnCTL1 register TPnIOC0 register TPnCCR0 register Initial setting of these registers is performed before setting the TPnCE bit to...

Page 362: ...tion with the next count up timing The INTTPnCC0 signal is generated and the output of the TOPn0 pin is inverted At this time an overflow interrupt request signal INTTPnOV is not generated nor is the...

Page 363: ...to the CCR0 buffer register as soon as the TPnCCR0 register has been rewritten Consequently the value of the 16 bit counter that is compared is D2 Because the count value has already exceeded D2 howe...

Page 364: ...is generated once per cycle At the same time the output of the TOPn1 pin is inverted The TOPn1 pin outputs a square wave with the same cycle as that output by the TOPn0 pin CCR0 buffer register TPnCC...

Page 365: ...the count value of the 16 bit counter does not match the value of the TPnCCR1 register Consequently the INTTPnCC1 signal is not generated nor is the output of the TOPn1 pin changed FFFFH 16 bit count...

Page 366: ...566EE1V2UM00 Figure 11 7 Timing chart when D01 D11 FFFFH 16 bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal TPnCCR1 register TOPn1 pin output INTTPnCC1 signal D01 D11 D0...

Page 367: ...external event count mode Figure 11 9 Basic timing in external event count mode Caution This figure shows the basic timing when the rising edge is specified as the valid edge of the external event co...

Page 368: ...it counter is cleared to 0000H and a compare match interrupt request signal INTTPnCC0 is generated The INTTPnCC0 signal is generated each time the valid edge of the external event count input has been...

Page 369: ...wever the set value of the TPnCCR1 register is transferred to the CCR1 buffer register When the count value of the 16 bit counter matches the value of the CCR1 buffer register a compare match interrup...

Page 370: ...he external event counter mode is started the first interrupt INTTPnCC0 INTTPnCC1 occurs upon the first timer overflow TPnCNT FFFFH 0000H but not with the first external count event Afterwards the fol...

Page 371: ...er initial setting TPnCTL0 register TPnCKS0 to TPnCKS2 bits TPnCTL1 register TPnIOC0 register TPnIOC2 register TPnCCR0 register Initial setting of these registers is performed before setting the TPnCE...

Page 372: ...d edge of the external event count signal has been detected The 16 bit counter is cleared to 0000H in synchronization with the next count up timing and the INTTPnCC0 signal is generated At this time t...

Page 373: ...been rewritten Consequently the value that is compared with the 16 bit counter is D2 Because the count value has already exceeded D2 however the 16 bit counter counts up to FFFFH overflows and then c...

Page 374: ...the output signal of the TOPn1 pin is inverted Figure 11 12 Timing chart when D01 D11 CCR0 buffer register TPnCE bit TPnCCR0 register 16 bit counter TPnCCR1 register CCR1 buffer register Clear Match...

Page 375: ...not generated because the count value of the 16 bit counter and the value of the TPnCCR1 register do not match Nor is the output signal of the TOPn1 pin changed Figure 11 13 Timing chart when D01 D11...

Page 376: ...rating a software trigger instead of using the external trigger When using a software trigger a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOPn0 p...

Page 377: ...hen the 16 bit counter counts next time after its count value matches the value of the CCR0 buffer register and the 16 bit counter is cleared to 0000H The compare match interrupt request signal INTTPn...

Page 378: ...rol register 1 TPnCTL1 0 1 0 0 0 0 TPnCTL0 Select count clockNote 0 Stop counting 1 Enable counting 0 1 0 1 0 1 TPnCKS2 TPnCKS1 TPnCKS0 TPnCE 0 0 1 0 1 0 0 TPnCTL1 0 Operate on count clock selected by...

Page 379: ...ntrol register 1 TPnIOC1 and TMPn option register 0 TPnOPT0 are not used in the external trigger pulse output mode 0 0 0 0 0 1 TPnIOC0 0 Disable TOPn0 pin output 1 Enable TOPn0 pin output Settings of...

Page 380: ...e 1 2 FFFFH 16 bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output External trigger input TIPn0 p...

Page 381: ...it 1 Trigger wait status TPnCCR1 register write processing is necessary only when the set cycle is changed When the counter is cleared after setting the value of the TPnCCRm register is transferred to...

Page 382: ...written to the TPnCCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16 bit counter and is used as the value compared with the 16 bit counter To write th...

Page 383: ...1 to the TPnCCR1 register If the set value of the TPnCCR0 register is FFFFH 100 output cannot be produced Count clock 16 bit counter TPnCE bit TPnCCR0 register TPnCCR1 register INTTPnCC0 signal INTTPn...

Page 384: ...e trigger is detected immediately before the INTTPnCC1 signal is generated the INTTPnCC1 signal is not generated and the 16 bit counter is cleared to 0000H and continues counting The output signal of...

Page 385: ...he trigger is detected immediately before the INTTPnCC0 signal is generated the INTTPnCC0 signal is not generated The 16 bit counter is cleared to 0000H the TOPn1 pin is asserted and the counter conti...

Page 386: ...ounter matches the value of the TPnCCR1 register Usually the INTTPnCC1 signal is generated in synchronization with the next count up after the count value of the 16 bit counter matches the value of th...

Page 387: ...enerated to output the pulse When the software trigger is used the TOPn0 pin outputs the active level while the 16 bit counter is counting and the inactive level when the counter is stopped waiting fo...

Page 388: ...ck cycle Active level width Set value of TPnCCR0 register Set value of TPnCCR1 register 1 Count clock cycle The compare match interrupt request signal INTTPnCC0 is generated when the 16 bit counter co...

Page 389: ...ontrol register 1 TPnCTL1 0 1 0 0 0 0 TPnCTL0 Select count clockNote 0 Stop counting 1 Enable counting 0 1 0 1 0 1 TPnCKS2 TPnCKS1 TPnCKS0 TPnCE 0 0 1 0 1 0 0 TPnCTL1 0 Operate on count clock selected...

Page 390: ...k cycle Note TMPn I O control register 1 TPnIOC1 and TMPn option register 0 TPnOPT0 are not used in the one shot pulse output mode 0 0 0 0 0 1 TPnIOC0 0 Disable TOPn0 pin output 1 Enable TOPn0 pin out...

Page 391: ...tial setting of these registers is performed before setting the TPnCE bit to 1 The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting has been started TPnCE bit 1 Trigger wait status Co...

Page 392: ...ch set value is reflected as soon as the register has been rewritten and compared with the count value The counter counts up to FFFFH and then counts up again from 0000H When the count value matches D...

Page 393: ...of the 16 bit counter matches the value of the TPnCCR1 register Usually the INTTPnCC1 signal is generated when the 16 bit counter counts up next time after its count value matches the value of the TP...

Page 394: ...cle of the PWM waveform as half its cycle is output from the TOPn0 pin Figure 11 21 Configuration in PWM output mode CCR0 buffer register TPnCE bit TPnCCR0 register 16 bit counter TPnCCR1 register CCR...

Page 395: ...the 16 bit counter is cleared to 0000H The compare match interrupt request signal INTTPnCC0 is generated when the 16 bit counter counts next time after its count value matches the value of the CCR0 b...

Page 396: ...TPnCKS1 TPnCKS0 TPnCE 0 0 0 0 0 TPnCTL1 1 0 0 TPnMD2 TPnMD1 TPnMD0 TPnEEE TPnEST 1 0 0 PWM output mode 0 0 0 0 0 1 TPnIOC0 0 Disable TOPn0 pin output 1 Enable TOPn0 pin output Setting of output level...

Page 397: ...and TPnCCR1 If D0 is set to the TPnCCR0 register and D1 to the TPnCCR1 register the cycle and active level of the PWM waveform are as follows Cycle D0 1 Count clock cycle Active level width D1 Count...

Page 398: ...utput mode 1 2 FFFFH 16 bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output D10...

Page 399: ...CCRm register is transferred to the CCRm buffer register START Setting of TPnCCR1 register 1 Count operation start flow 2 TPnCCR0 TPnCCR1 register setting change flow Setting of TPnCCR0 register When...

Page 400: ...ter To change only the active level width duty factor of the PWM waveform only the TPnCCR1 register has to be set After data is written to the TPnCCR1 register the value written to the TPnCCRm registe...

Page 401: ...TPnCCR1 register If the set value of the TPnCCR0 register is FFFFH 100 output cannot be produced Count clock 16 bit counter TPnCE bit TPnCCR0 register TPnCCR1 register INTTPnCC0 signal INTTPnCC1 sign...

Page 402: ...ounter matches the value of the TPnCCR1 register Usually the INTTPnCC1 signal is generated in synchronization with the next counting up after the count value of the 16 bit counter matches the value of...

Page 403: ...TPnCCS1 bits Figure 11 25 Configuration in free running timer mode TPnCCR0 register capture TPnCE bit TPnCCR1 register compare 16 bit counter TPnCCR1 register compare TPnCCR0 register capture Output...

Page 404: ...s cleared to 0000H and continues counting At this time the overflow flag TPnOPT0 TPnOVF bit is also set to 1 Clear the overflow flag to 0 by executing the CLR instruction by software The TPnCCRm regis...

Page 405: ...t request signal INTTPnOV at the next clock is cleared to 0000H and continues counting At this time the overflow flag TPnOPT0 TPnOVF bit is also set to 1 Clear the overflow flag to 0 by executing the...

Page 406: ...PnCKS0 TPnCE 0 0 0 1 0 0 TPnCTL1 1 0 1 TPnMD2 TPnMD1 TPnMD0 TPnEEE TPnEST 1 0 1 Free running mode 0 Operate with count clock selected by TPnCKS0 to TPnCKS2 bits 1 Count on external event count input s...

Page 407: ...t counter when the valid edge input to the TIPnm pin is detected When the registers function as compare registers and when Dm is set to the TPnCCRm register the INTTPnCCm signal is generated when the...

Page 408: ...free running timer mode compare function 1 2 FFFFH 16 bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register INTTPnCC1 signal TOPn1 pin output INTTPnOV signal...

Page 409: ...PT0 TPnCCR0 TPnCCR1 Initial setting of these registers is performed before setting the TPnCE bit to 1 The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting has been started TPnCE bit 1...

Page 410: ...mer mode capture function 1 2 FFFFH 16 bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register INTTPnCC0 signal TIPn1 pin input TPnCCR1 register INTTPnCC1 signal INTTPnOV signal TPnOVF bit D00 00...

Page 411: ...TPnOPT0 Initial setting of these registers is performed before setting the TPnCE bit to 1 The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting has been started TPnCE bit 1 START Execu...

Page 412: ...TPnCCm signal is detected The set value for re setting the TPnCCRm register can be calculated by the following expression where Dm is the interval period Compare register default value Dm 1 Value set...

Page 413: ...CCRm register in synchronization with the INTTPnCCm signal and calculating the difference between the read value and the previously read value FFFFH 16 bit counter 0000H TPnCE bit TIPn0 pin input TPnC...

Page 414: ...d the TPnCCR0 register Read the overflow flag If the overflow flag is 1 clear it to 0 Because the overflow flag is 1 the pulse width can be calculated by 10000H D01 D00 4 Read the TPnCCR1 register Rea...

Page 415: ...overflow flag to 0 4 Read the TPnCCR0 register Read the TPnOVF0 flag If the TPnOVF0 flag is 1 clear it to 0 Because the TPnOVF0 flag is 1 the pulse width can be calculated by 10000H D01 D00 5 Read th...

Page 416: ...ag If the overflow flag is 1 set only the TPnOVF1 flag to 1 and clear the overflow flag to 0 Because the overflow flag is 1 the pulse width can be calculated by 10000H D01 D00 5 Read the TPnCCR1 regis...

Page 417: ...is measured in the free running timer mode 1 Read the TPnCCRm register setting of the default value of the TIPnm pin input 2 An overflow occurs Nothing is done by software 3 An overflow occurs a seco...

Page 418: ...TIPnm pin input 2 An overflow occurs Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing 3 An overflow occurs a second time Increment 1 the overflow co...

Page 419: ...software may judge that no overflow has occurred even when an overflow actually has occurred If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is clea...

Page 420: ...or TIPn1 pin as the capture trigger input pin Specify No edge detected by using the TPnIOC1 register for the unused pins When an external clock is used as the count clock measure the pulse width of th...

Page 421: ...If the valid edge is not input to the TIPnm pin even when the 16 bit counter counted up to FFFFH an overflow interrupt request signal INTTPnOV is generated at the next count clock and the counter is c...

Page 422: ...TPnCTL0 Select count clockNote 0 Stop counting 1 Enable counting 0 1 0 1 0 1 TPnCKS2 TPnCKS1 TPnCKS0 TPnCE 0 0 0 1 0 0 TPnCTL1 1 1 0 TPnMD2 TPnMD1 TPnMD0 TPnEEE TPnEST 1 1 0 Pulse width measurement m...

Page 423: ...pture compare registers 0 and 1 TPnCCR0 and TPnCCR1 These registers store the count value of the 16 bit counter when the valid edge input to the TIPnm pin is detected Note TMPn I O control register 0...

Page 424: ...PnIOC1 TPnIOC2 TPnOPT0 Initial setting of these registers is performed before setting the TPnCE bit to 1 The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting has been started TPnCE bi...

Page 425: ...the above chart Therefore software may judge that no overflow has occurred even when an overflow actually has occurred If execution of the CLR instruction conflicts with occurrence of an overflow when...

Page 426: ...ut One shot pulse output mode One shot pulse output PWM output mode PWM output Free running timer mode Square wave output only when compare function is used Pulse width measurement mode Table 11 12 Tr...

Page 427: ...irst captured counter value of the capture registers TPnCCR0 TPnCCR i e after the timer is enabled TPnCTL0 TPnCE 1 may be FFFFH instead of 0000H if the chosen count clock of the TMP is not the maximum...

Page 428: ...428 Chapter 11 16 bit Timer Event Counter P TMP Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 429: ...Z can be used as Interval timer Free running timer Features summary Special features of the TMZ are One of six peripheral clocks can be selected One reload register Two readable counter registers When...

Page 430: ...n as a non zero value is written to the reload register TZnR and copied to the reload buffer When the counter reaches zero it generates an INTTZnUV interrupt reloads its start value from the reload bu...

Page 431: ...iew Register name Shortcut Address Timer Z synchronized read register TZnCNT0 base Timer Z non synchronized read register TZnCNT1 base 2H Timer Z reload register TZnR base 4H Timer Z control register...

Page 432: ...7 6 5 4 3 2 1 0 TZCE 0 0 0 0 TZCKS2 TZCKS1 TZCKS0 R W R R R R R W R W R W Table 12 3 TZnCTL register contents Bit position Bit name Function 7 TZCE Timer Z counter enable 0 Disable count operation the...

Page 433: ...counter and therefore in doubt Access This register is read only in 16 bit units Address base 2H Initial Value 0000H This register is cleared by any reset and when TZnCTL TZCE 0 Note The value read fr...

Page 434: ...0000H This register is cleared by any reset and when TZnCTL TZCE 0 Note 1 TZnR can only be written when TZnCTL TZCE 1 2 The load value must be non zero 0001H FFFFH 3 To operate the timer in free runni...

Page 435: ...k a jitter of maximum 1 period of PCLK2 may be applied to the TZnCNT counter s count clock input 12 3 1 Steady operation Steady operation is illustrated in the following figure Figure 12 2 Reload timi...

Page 436: ...n as the counter clock TZnCTL TZCKS 0 the first and all following interrupts occur after Tinterval TZnR 1 where TZnR contents of register TZnR An uncertainty exists for the first interval length if a...

Page 437: ...4 for the free assignable Input Output channels x 0 1 for bit index i e one of the 2 counters of each Timer Gn y 0 to 5 for all of the 6 capture compare channels 13 1 Features of Timer G The timers Gn...

Page 438: ...flow interrupt requests 2 types In free run mode the INTTMGn0 INTTMGn1 interrupt is generated when the count value of TMGn0 TMGn1 toggles from FFFFH to 0000H In match and clear mode the INTTMGn0 INTTM...

Page 439: ...PLK0 8 fSCPLK0 16 fSCPLK0 32 fSCPLK0 64 fSCPLK0 128 fCOUNT1 Noise Elimination Edge Detection Noise Elimination Edge Detection Noise Elimination Edge Detection Noise Elimination Edge Detection Noise El...

Page 440: ...n The basic configuration is shown below Table 13 1 Timer Gn configuration list Note fSPCLK0 Internal peripheral clock Count clock Register R W Generated interrupt signal Capture trigger Timer output...

Page 441: ...ime base status register TMGSTn base 6H Timer Gn count register 0 TMG00 base 8H Timer Gn count register 1 TMG01 base AH Timer Gn capture compare register 0 GCC00 base CH Timer Gn capture compare regis...

Page 442: ...ol 0 operation Stop the capture registers and TMGSTn register are cleared the TOGnm pins are inactive all the time 1 operation enable Note At least 7 peripheral clocks fSPCLK0 are needed to start the...

Page 443: ...set the rewriting of this bits are prohibited Simultaneously writing with the POWERn bit is allowed 3 1 CLRGnx Specifies software clear for TMGnx 0 Continue TMGnx operation 1 Clears 0 the count value...

Page 444: ...IEGn41 IEGn40 R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 IEGn31 IEGn30 IEGn21 IEGn20 IEGn11 IEGn10 IEGn01 IEGn00 R W R W R W R W R W R W R W R W Table 13 5 TMGCMn register contents Bit position...

Page 445: ...W R W R W R W 7 6 5 4 3 2 1 0 SWFGn2 ALVGn2 CCSGn2 0 SWFGn1 ALVGn1 CCSGn1 0 R W R W R W R W R W R W R W R W Table 13 6 OCTLGn register contents Bit position Bit name Function 15 11 7 3 SWFGnm Fixes t...

Page 446: ...e Access These registers can be read written in 16 bit units Address TMGn0 base 8H TMGn1 base AH Initial Value 0000H This register is cleared by any reset 7 6 5 4 3 2 1 0 ENFGn1 ENFGn2 CCFGn5 CCFGn4 C...

Page 447: ...Pin TIGn0 TIGn5 Compare mode In the compare register mode GCCn0 GCCn5 detects match with TMGn0 TMGn1 and clears the assigned Timebase So this match and clear mode is used to reduce the number of vali...

Page 448: ...to 4 of the TMGCMnH register 0 When the TBGnm bit 1 these registers hold the value of TMGn1 Compare mode In compare mode these registers represent the actual compare value and the TOGnm Output m 1 to...

Page 449: ...ck is set to fSPCLK0 2 However 0FFFH is set in GCCn0 Similar delays are added also when a transition is made from the active to inactive level So a relative pulse width is guaranteed Figure 13 2 Timin...

Page 450: ...the value of the GCCn0 register is FFFFH 2 An interrupt is generated only when the value of the GCCn0 register is not FFFFH 3 The setting of the CCSGnm bit in combination with the SWFGnm bit sets the...

Page 451: ...ons In this mode the 2 counter TMGn0 and TMGn1 are counting up from 0000H to FFFFH generates an overflow and start again In the match and clear mode which is described in Chapter 13 8 on page 462 the...

Page 452: ...and an edge detection interrupt INTCCGny is output 2 When the counter overflows an overflow interrupt INTTMGn0 or INTTMGn1 is generated 3 If an overflow has occurred between capture operations the CC...

Page 453: ...ws an image In actual circuitry 3 to 4 periods of the count up signal are required from the input of a waveform to TIGn0 until a capture interrupt is output 0000H 0001H D0 D1 TMGn0 D0 GCCn0 C ount sta...

Page 454: ...quired from edge input until an interrupt signal is output and capture operation is performed The timing chart is shown below Basic settings x 0 1 and y 0 to 5 Figure 13 4 Timing of capture trigger ed...

Page 455: ...to prevent the initial TIGny level from being recognized as an edge by mistake The timing chart for starting edge detection is shown below Basic settings x 0 1 and y 0 to 5 Figure 13 5 Timing of star...

Page 456: ...data to GCCnm 4 Start timer operation by setting POWERn and TMGn0E or TMGn1E Compare Operation 1 When the value of the counter matches the value of GCCnm m 0 to 4 a match interrupt INTCCGnm is output...

Page 457: ...NTTMGn1 are activated when the value of the counter changes from FFFFH to 0000H d When GCCnm is rewritten during operation When GCCn1 is rewritten from 5555H to AAAAH TMGn0 is selected as the counter...

Page 458: ...eration by setting POWERn bit and TMGn0E bit or TMGn1E bit PWM operation 1 When the value of the counter matches the value of GCCnm a match interrupt INTCCGnm is output 2 When the counter overflows an...

Page 459: ...d to the inactive level The figure below shows the state of TOGn1 when 0000H is set in GCCn1 and TMGn0 is selected Figure 13 9 Timing when 0000H is set in GCCnm free run GCCn1 and TMGn0 are selected N...

Page 460: ...eriod immediately after each counter overflow except the first overflow The figure shows the state of TOGn1 when FFFFH is set in GCCn1 and TMGn0 is selected Figure 13 10 Timing when FFFFH is set in GC...

Page 461: ...n1 and TMGn0 are selected If GCCn1 is rewritten to AAAAH after the second INTCCGn1 is generated as shown in the figure above AAAAH is reloaded to the GCCn1 register when the next overflow occurs The n...

Page 462: ...o CSE10 TMGn1 bits or CSE02 to CSE00 TMGn0 bits 3 Select a valid TIGnm edge with the IEGnm1 and IEGnm0 bit A rising edge falling edge or both edges can be selected 4 Set an upper limit on the value of...

Page 463: ...ear events occur between captures a software based measure needs to be taken to count INTCCGn0 or INTCCGn5 c When 0000H is set in GCCn0 or GCCn5 match and clear When 0000H is set in GCCn0 GCCn5 the va...

Page 464: ...GCCn0 or GCCn5 4 Write data to GCCnm 5 Start timer operation by setting the POWERn bit and TMGxE bit x 0 1 Operation 1 When the value of the counter matches the value of GCCnm a match interrupt INTCCG...

Page 465: ...CCn5 match and clear When FFFFH is set in GCCn0 or GCCn5 operation equivalent to the free run mode is performed When an overflow occurs INTTMGn0 or INTTMGn1 is generated but INTCCGn0 or INTCCGn5 is no...

Page 466: ...ive write access during operation for rewriting the GCCny register you have to wait for minimum 7 peripheral clocks periods fSPCLK0 3 PMW output match and clear Basic settings m 1 to 4 Note The PWM mo...

Page 467: ...eration by setting POWERn bit and TMGn0E bit or TMGn1E bit Operation of PWM match and clear 1 When the value of the counter matches the value of GCCnm a match interrupt INTCCGnm is output Caution Do n...

Page 468: ...er does not operate The waveform of INTCCGn0 INTCCGn5 varies depending on whether the count clock is the reference clock or the sampling clock a When FFFFH is set in GCCn0 or GCCn5 match and clear Whe...

Page 469: ...the inactive level The figure below shows the state of TOGn1 when 0000H is set in GCCn1 and TMGn0 is selected Note however that 0FFFH is set in GCCn0 Figure 13 16 Timing when 0000H is set in GCCnm mat...

Page 470: ...only one clock period immediately after each match and clear event excluding the first match and clear event The figure below shows the state of TOGn1 when 0FFFH is set in GCCn0 and GCCn1 and TMGn0 i...

Page 471: ...continues outputting the active level immediately after the first match and clear event until count operation stops The figure shows the state of TOGn1 when 0FFFH is set in GCCn0 1FFFH is set in GCCn1...

Page 472: ...during operation match and clear If GCCn1 is rewritten to 0AAAH after the second INTCCGn1 is generated as shown in the figure above 0AAAH is reloaded to the GCCn1 register when the next overflow occur...

Page 473: ...ng This is because the count up signal of the counter is used for sampling timing The upper figure below shows the timing chart for performing edge detection The lower figure below shows the timing ch...

Page 474: ...L and OCTLGnH registers These bits configure the active level of the TOGnm pins m 1 to 4 2 When POWERn bit and TMGxE bit are set x 0 1 The rewriting of ALVGnm is prohibited m 1 to 4 These bits configu...

Page 475: ...pin y 0 to 5 until a capture interrupt is output When TMGxE x 0 1 is set earlier or simultaneously with POWERn bit than the Timer Gn needs 7 peripheral clocks periods fSPCLK0 to start counting When TM...

Page 476: ...476 Chapter 13 16 bit Multi Purpose Timer G TMG Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 477: ...ain oscillator is switched off in order to save power WT1 WT1 is clocked by the interrupts generated by WT0 It can for example generate an interrupt every hour or whatever wake up time is required Thi...

Page 478: ...Can operate in all power save modes Clock correction in stand by mode by means of the Watch Calibration Timer In debug mode the counters WT0 and WT1 can be stopped at breakpoint Special features of t...

Page 479: ...e by setting WTnCTL WTCE to 1 As soon as the counters are enabled it is possible to write a start value to the reload registers WT0R and WT1R WCT is a capture compare timer In this application it meas...

Page 480: ...tch Timer After reset the timer is also stopped When WT0 is enabled and a non zero reload value is specified the counter decreases with every rising edge of WTCLK When the counter reaches zero the int...

Page 481: ...counter WT0 triggers the capture operation At every INTWT0UV the count value is captured and the interrupt INTTM00 is generated From the counter difference between two consecutive capture events the a...

Page 482: ...interval from counter start to the first underflow takes at least four clock cycles more than the following intervals For details refer to Watch Timer start up on page 486 Table 14 2 WTn registers ov...

Page 483: ...stantaneous value immediately with the risk that this value is just being updated by the counter and therefore in doubt Access This register is read only in 16 bit units Address base 2H Initial Value...

Page 484: ...Note 1 WTnR can only be written when WTnCTL WTCE 1 counter enabled 2 The load value must be non zero 0001H FFFFH 3 The contents of this register is automatically copied to the reload buffer The counte...

Page 485: ...he reload buffer The counters WTn reload their start value from the buffer upon underflow This is illustrated in the following figure Figure 14 2 Reload timing and interrupt generation D0 and D1 are t...

Page 486: ...wn in the following diagram Figure 14 3 WT1 start up timing To start the counter in a deterministic way the above actions have to be synchronized to the WT1 input clock which is INTWT0UV For that purp...

Page 487: ...one second tick However it may happen that the write to WT1R is delayed because of other circumstances nested interrupts DMA transfers etc and may happen after S W counter state 3 Thus WT1 would star...

Page 488: ...T registers overview Register name Shortcut Address WCT timer counter read register TM00 base WCT capture compare register CR000 base 2H WCT mode control register TMC00 base 6H WCT prescaler mode regi...

Page 489: ...he OVF00 bit is set when the counter reaches FFFFH and once more when the counter continues with 0000H Clearing OVF00 within that time has no effect 7 6 5 4 3 2 1 0 0 0 0 0 TMC003 TMC002 0 OVF00 R R R...

Page 490: ...All other bits are initialized as zero and must not be changed Note 1 If both edges of INTWT0UV are specified as valid INTWT0UV interval measurement is not possible 2 Stop the timer before changing E...

Page 491: ...2 If both the rising edge and falling edge are specified as valid for the INTWT0UV signal the interval measurement does not work 3 Be sure to set bits 7 to 3 to 0 7 6 5 4 3 2 1 0 0 0 0 0 0 X CRC001 C...

Page 492: ...d Access In compare mode this register can be read written in 16 bit units In capture mode it cannot be written Address base 4H Initial Value 0000H This register is cleared by any reset Note Stop the...

Page 493: ...0 For further details refer to Clock Generator on page 129 The measured INTWT0UV interval time gives an indication about the accuracy of the sub or ring oscillator A correction value can be calculate...

Page 494: ...o scale but illustrates the operation Figure 14 4 Timing in free running mode As shown in the figure the interrupt INTTM00 can be used as a trigger for reading the register CR000 The interval duration...

Page 495: ...apture signal PRM00 ES00 1 0 0100 0000B Rising edge The following figure is not to scale but illustrates the operation Figure 14 5 Timing in restart mode As shown in the figure the present value of CR...

Page 496: ...496 Chapter 14 Watch Timer WT Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 497: ...chdog Timer clock WDTCLK This clock can be derived from the main oscillator the ring oscillator or the sub oscillator It s frequency can be identical with the frequency of the source clock or a fracti...

Page 498: ...1 generate reset request RESWDT The mode is defined by the bit WDTM WDTMODE The mode can only be changed after SYSRESWDT that means after external RESET or Power On Clear 1 Watchdog Timer mode 0 gene...

Page 499: ...Timer clock The Watchdog Timer clock WDTCLK is generated by the Clock Generator It can be derived from the main ring or sub oscillator The generation of WDTCLK is controlled by the WCC register of th...

Page 500: ...started it cannot be reprogrammed or stopped unless the next reset SYSRES or SYSRESWDT occurs SYSRES SYSRES is generated by all reset sources SYSRES does not reset the register WDTM That means the ti...

Page 501: ...Their protection status is indicated in the WDTM register Note Only byte access is supported for the registers WDCS WCMD and WDTM The registers are allocated at even addresses Thus they cannot be wri...

Page 502: ...gister is initialized by SYSRESWDT and SYSRES Note The WDCS register must be considered in conjunction with the WCC register of the Clock Generator The source and frequency of WDTCLK are defined in th...

Page 503: ...ter interval 1 Write one byte to the WCMD register the value is ignored 2 Immediately after that write one byte with the desired value of WDCS 2 0 to the WDCS register The write operation resets the w...

Page 504: ...r is running you can also write to this register but the write operation does not change the register contents WDTM LOCK_TM 1 When the timer is running the write access resets the counter To write to...

Page 505: ...ee also Write Protected Registers on page 124 With this method the protected registers can only be rewritten in a specific sequence Illegal write access to a protected register is inhibited The follow...

Page 506: ...PRERR flag is set Access This register can be read written in 8 bit or 1 bit units After a write access the register is cleared Address base 6H Initial Value 00H This register is cleared by SYSRESWDT...

Page 507: ...rror Framing error Overrun error Interrupt sources 3 Reception complete interrupt INTUAnR This interrupt occurs upon transfer of receive data from the shift register to receive buffer register n after...

Page 508: ...ck diagram of the UARTAn is shown below Figure 16 1 Block diagram of Asynchronous Serial Interface UARTAn Note For the configuration of the baud rate generator see Figure 16 11 on page 533 UARTAn cons...

Page 509: ...register cannot be manipulated directly 7 UARTAn receive data register UAnRX The UAnRX register is an 8 bit register that holds receive data When 7 characters are received 0 is stored in the highest b...

Page 510: ...Shortcut Address UARTAn control register 0 UAnCTL0 base UARTAn control register 1 UAnCTL1 base 1H UARTAn control register 2 UAnCTL2 base 2H UARTAn option control register 0 UAnOPT0 base 3H UARTAn sta...

Page 511: ...AnTDL bit 1 6 UAnTXE Transmit operation disable enable 0 Disable transmit operation 1 Enable transmit operation To start transmission set the UAnPWR bit to 1 and then set the UAnTXE bit to 1 To stop t...

Page 512: ...rity output Odd parity check 1 1 Even parity output Even parity check This register is rewritten only when the UAnPWR bit 0 or the UAnTXE bit the UAnRXE bit 0 If Reception with 0 parity is selected du...

Page 513: ...er that controls the serial transfer operation of the UARTAn register Access This register can be read written in 8 bit or 1 bit units Address base 3H Initial Value 14H This register is cleared by any...

Page 514: ...is always read Set the UAnSTT bit after setting the UAnPWR bit UAnTXE bit 1 a Before starting the SBF transmission by UAnOPT0 UAnSTT 1 make sure that no data transfer is ongoing that means check that...

Page 515: ...3 2 1 0 UAnTSF 0 0 0 0 UAnPE UAnFE UAnOVE R R W R W R W R W R Wa a These bits can only be cleared by writing They cannot be set by writing 1 even if 1 is written the value is retained R Wa R Wa Table...

Page 516: ...st bit of the receive data stop bits is checked regardless of the value of the UAnCTL0 UAnSL bit The UAnFE bit can be both read and written but it can only be cleared by writing 0 to it and it cannot...

Page 517: ...transferred to bits 7 to 1 of the UAnRX register and the LSB always becomes 0 When an overrun error UAnOVE occurs the receive data at this time is not transferred to the UAnRX register and is discard...

Page 518: ...RE is generated instead of INTUAnR No reception complete interrupt request signal is generated in the reception disabled status 2 Receive error interrupt request signal INTUAnRE A receive error interr...

Page 519: ...B LSB first transfer are performed using the UAnCTL0 register Moreover control of UART output inverted output for the TXDAn bit is performed using the UAnOPT0 UAnTDL bit Start bit 1 bit Character bits...

Page 520: ...ata length LSB first odd parity 2 stop bits transfer data 36H e 8 bit data length LSB first no parity 1 stop bit transfer data 87H 1 data frame Start bit D7 D6 D5 D4 D3 D2 D1 D0 Parity bit Stop bit 1...

Page 521: ...aster transmits a frame with baud rate information and the slave receives it and corrects the baud rate error Therefore communication is possible when the baud rate error in the slave is 15 or less Fi...

Page 522: ...OVE UAnSTR UAnPE and UAnSTR UAnFE bits is suppressed and UART communication error detection processing and UARTAn receive shift register and data transfer of the UAnRX register are not performed The U...

Page 523: ...status is set by setting the SBF reception trigger UAnOPT0 UAnSTR bit to 1 In the SBF reception wait status similarly to the UART reception wait status the RXDAn pin is monitored and start bit detecti...

Page 524: ...rmal SBF reception detection of stop bit in more than 10 5 bits b SBF reception error detection of stop bit in 10 5 or fewer bits UAnSRF 1 2 3 4 5 6 11 5 7 8 9 10 11 INTUAnR interrupt UA0SRF 1 2 3 4 5...

Page 525: ...port to check that reception is enabled at the transmit destination The data in the UAnTX register is transferred to the UARTAn transmit shift register upon the start of the transmit operation A trans...

Page 526: ...NTUAnT An efficient communication rate is realized by writing the data to be transmitted next to the UAnTX register during transfer Caution During continuous transmission execution perform initializat...

Page 527: ...n timing transmission end Start Data 1 Data 1 TXDAn UAnTX Transmission shift register INTUAnT UAnTSF Data 2 Data 2 Data 1 Data 3 Parity Stop Start Data 2 Parity Stop Start Start Data n 1 Data n 1 Data...

Page 528: ...e receive operation starts and serial data is saved to the UARTAn receive shift register according to the set baud rate When the reception complete interrupt request signal INTUAnR is output upon rece...

Page 529: ...as been generated and clear the UAnPWR or UAnRXE bit to 0 If the UAnPWR or UAnRXE bit is cleared to 0 before the INTUAnR signal is generated the read value of the UAnRX register cannot be guaranteed 4...

Page 530: ...types and operations Caution When using the LIN function fix the UAnPS1 and UAnPS0 bits of the UAnCTL0 register to 00 The parity bit is used to detect bit errors in the communication data Normally th...

Page 531: ...ta 1 During reception The number of bits whose value is 1 among the receive data including the parity bit is counted and if it is an even number a parity error is output 3 0 parity During transmission...

Page 532: ...see Figure 16 10 See Base clock on page 533 regarding the base clock Moreover since the circuit is as shown in Figure 16 9 the processing that goes on within the receive operation is delayed by 3 cloc...

Page 533: ...r a Base clock When the UAnCTL0 UAnPWR bit is 1 the clock selected by the UAnCTL1 UAnCKS 2 0 bits is supplied to the 8 bit counter This clock is called the base clock When the UAnPWR bit 0 fUCLK is fi...

Page 534: ...nitial Value 00H This register is cleared by any reset Caution Clear the UAnCTL0 UAnPWR bit to 0 before rewriting the UAnCTL1 register 7 6 5 4 3 2 1 0 0 0 0 0 0 UAnCKS2 UAnCKS1 UAnCKS0 R R R R R R W R...

Page 535: ...e UAnCTL2 register Note fUCLK clock frequency selected by UAnCTL1 UAnCKS 2 0 7 6 5 4 3 2 1 0 UAnBRS7 UAnBRS6 UAnBRS5 UAnBRS4 UAnBRS3 UAnBRS2 UAnBRS1 UAnBRS0 R R R R R R W R W R W Table 16 8 UAnCTL2 re...

Page 536: ...rate error during transmission must be within the error tolerance on the receiving side 2 The baud rate error during reception must satisfy the range indicated in 7 Allowable baud rate range during r...

Page 537: ...n the allowable error range using the following equation Target baud rate UAnCTL1 UAnCTL2 Effective baud rate bps Baud rate error bps Selector Divider Divider k 300 07H 128 68H 104 300 48 0 16 600 07H...

Page 538: ...e of UAnCTL2 UAnBRS 7 0 FL 1 bit data length Latch timing margin 2 clocks Minimum allowable transfer rate Therefore the maximum baud rate that can be received by the destination is as follows Similarl...

Page 539: ...ble 16 10 Maximum Minimum allowable baud rate error Note 1 The reception accuracy depends on the bit count in 1 frame the input clock frequency and the division ratio k The higher the input clock freq...

Page 540: ...rate during continuous transmission is as follows Transfer rate 11 FL 2 fUCLK 16 7 Cautions When the clock supply to UARTAn is stopped for example in IDLE or STOP mode the operation stops with each re...

Page 541: ...erface 3 interrupt request signals INTCBnT INTCBnR INTCBnRE Serial clock and data phase switchable Transfer data length selectable in 1 bit units between 8 and 16 bits Transfer data MSB first LSB firs...

Page 542: ...clock is generated by the dedicated baud rate generator BRGn Internal bus CBnCTL2 CBnCTL0 CBnSTR Controller INTCBnR INTCBnRE SOBn INTCBnT CBnTX SO latch Phase control Shift register CBnRX CBnCTL1 Phas...

Page 543: ...iew Register name Shortcut Address CSIBn control register 0 CBnCTL0 base CSIBn control register 1 CBnCTL1 base 1H CSIBn control register 2 CBnCTL2 base 2H CSIBn status register CBnSTR base 3H CSIBn re...

Page 544: ...register contents 1 2 Bit position Bit name Function 7 CBnPWR CSIBn operation disable enable 0 Disable CSIBn operation and reset the CSIBn registers 1 Enable CSIBn operation The CBnPWR bit controls t...

Page 545: ...n mode A communication operation can be started only when the CBnSCE bit is 1 Set the CBnSCE bit to 1 b In single reception mode Clear the CBnSCE bit to 0 before reading the receive data CBnRX registe...

Page 546: ...it 0 7 6 5 4 3 2 1 0 0 0 0 CBnCKP CBnDAP CBnCKS2 CBnCKS1 CBnCKS0 R W R W R W R W R W R W R W R W Table 17 4 CBnCTL1 register contents Bit position Bit name Function 4 3 CBnCKP CBnDAP Specification of...

Page 547: ...iming in relation to SCKBn Communication type 1 0 0 Communication type 2 0 1 Communication type 3 1 0 Communication type 4 1 1 D7 D6 D5 D4 D3 D2 D1 D0 SCKBn I O SIBn capture SOBn output D7 D6 D5 D4 D3...

Page 548: ...h the CBnTXE and CBnRXE bits 0 Note If the number of transfer bits is other than 8 or 16 prepare and use data stuffed from the LSB of the CBnTX and CBnRX registers 7 6 5 4 3 2 1 0 0 0 0 0 CBnCL3 CBnCL...

Page 549: ...other than 16 bits set the data to the CBnTX or CBnRX register starting from the LSB regardless of whether the transfer start bit is the MSB or LSB Any data can be set for the higher bits that are not...

Page 550: ...CBnOVE is set to 1 and the previous data in CBnRX will be overwritten with the new data 7 6 5 4 3 2 1 0 CBnTSF 0 0 0 0 0 0 CBnOVE R R W R W R W R W R W R W R W Table 17 7 CBnSTR register contents Bit...

Page 551: ...write the CSIBn transfer data Access This register can be read written in 16 bit units If the transfer data length is 8 bits the lower 8 bits of this register are read write in 8 bit units as the CBnT...

Page 552: ...led status 4 Set the CBnPWR bit to 1 to enable the CSIBn operation 5 Write transfer data to the CBnTX register transmission start 6 The reception complete interrupt request signal INTCBnR is output 7...

Page 553: ...In case the next transmit should be initiated immediately after the occurrence of the reception completion interrupt INTCBnR any write to the CBnTX register is ignored as long as the communication sta...

Page 554: ...enable the CSIBn operation 5 Perform a dummy read of the CBnRX register reception start trigger 6 The reception complete interrupt request signal INTCBnR is output 7 Set the CBnSCE bit to 0 to set the...

Page 555: ...e using the CBnDIR bit to set the transmission reception enabled status 4 Set the CBnPWR bit to 1 to enable the CSIBn operation 5 Write transfer data to the CBnTX register transmission start 6 The tra...

Page 556: ...BnPWR bit to 0 2 Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode 3 Set the CBnCTL0 CBnRXE bit to 1 at the same time as specifying the transfer mode using the CBnDIR bit to set the r...

Page 557: ...bit to set the reception enabled status 4 Set the CBnPWR bit 1 to enable CSIBn operation 5 Perform a dummy read of the CBnRX register reception start trigger 6 The reception complete interrupt request...

Page 558: ...o 1 at the same time as specifying the transfer mode using the CBnDIR bit to set the transmission reception enabled status 4 Set the CBnPWR bit to 1 to enable supply of the CSIBn operation 5 Write the...

Page 559: ...tted correctly but the third 96H fails 1 Data 55H is written by the CPU or DMA to CBnTX 2 The master issues the clock SCKBn and transmission of 55H starts 3 INTCBnT is generated and the next data AAH...

Page 560: ...t the same time as specifying the transfer mode using the CBnDIR bit to set the reception enabled status 4 Set the CBnPWR bit 1 to enable CSIBn operation 5 Perform a dummy read of the CBnRX register r...

Page 561: ...0 CBnDAP 0 Figure 17 5 ii Communication type 3 CBnCKP 1 CBnDAP 0 D6 D5 D4 D3 D2 D1 SCKBn SIBn capture Reg R W SOBn INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF D0 D7 D6 D5 D4 D3 D2 D1 D0 D7...

Page 562: ...l is not generated but the INTCBnR interrupt request signal is generated upon completion of communication 2 The INTCBnR interrupt occurs if reception is correctly completed and receive data is ready i...

Page 563: ...n is disabled CBnPWR bit 0 the SOBn pin output status is as follows Note 1 The SOBn pin output changes when any one of the CBnCTL0 CBnTXE CBnCTL0 CBnDIR bits and CBnCTL1 CBnDAP bit is rewritten 2 don...

Page 564: ...slave mode data cannot be correctly transmitted if the next transfer clock is input earlier than the CBnTX register is written START No Yes INTCBnT bit 1 Data to be transferred next exists END Yes No...

Page 565: ...cannot be correctly received if the next transfer clock is input earlier than the CBnRX register is read START No INTCBnR bit 1 Last data END Yes Yes No Initial setting CBnCTL0Note CBnCTL1 registers...

Page 566: ...transmission reception mode therefore programming without checking the CBnOVE flag is recommended START Initial setting CBnCTL0Note 1 CBnCTL1 registers etc Write CBnTX register start transfer END CBn...

Page 567: ...Set the CBnSCE bit to 1 in the initial setting START No Yes INTCBnT bit 1 Data to be transferred next exists END Yes No Initial setting CBnCTL0Note CBnCTL1 registers etc Write CBnTX register start tr...

Page 568: ...on can be prevented by executing the flow marked in the above flowchart Before resuming communication set the CBnCTL0 CBnSCE bit to 1 and read dummy data from the CBnRX register START END No No Yes IN...

Page 569: ...ting START END No No INTCBnT bit 1 Yes No INTCBnT bit 1 Yes Initial setting CBnCTL0Note CBnCTL1 registers etc Write CBnTX register CBnRX register read Yes Yes Is data completely received last data No...

Page 570: ...1V2UM00 17 7 Baud Rate Generator 17 7 1 Overview Each CSIBSn interface is equipped with a dedicated baud rate generator BGnCS1 BGnCS0 PRSCMn Match detector 1 2 BRGnOUT 8 bit timer counter Selector 1 1...

Page 571: ...Sn 1 0 bits before setting the BGCEn bit to 1 Table 17 9 BRGn registers overview Register name Shortcut Address BRGn prescaler mode register PRSMn BRG_base BRGn prescaler compare register PRSCMn BRG_b...

Page 572: ...RSCMn register before setting the PRSMn BGCEn bit to 1 17 7 3 Baud rate calculation The transmission reception clock is generated by dividing the main clock The baud rate generated from the main clock...

Page 573: ...al interface with the following features Supports Master and Slave mode 8 bit data transfer Transfer speed up to 100 kbit s Standard Mode up to 400 kbit s Fast Mode I2 C root clock sources from main o...

Page 574: ...last step Table 17 3 shows how to set up the registers for activating I2 C0 and I2 C1 from different pin groups Table 18 1 I2 C interface pins set up I2 Cn PFSR0 register Pins and pin group Register s...

Page 575: ...nator Match signal IIC shift register n IICn SO latch Start condition generator Data hold time correction circuit Acknowledge output circuit Wake up controller N ch open drain output Acknowledge detec...

Page 576: ...al transmit and receive operations 2 Slave address register n SVAn The SVAn register sets local addresses when in slave mode 3 SO latch The SO latch is used to retain the output level of the SDAn pin...

Page 577: ...the sampling clock 9 Serial clock wait controller This circuit controls the wait timing 10 ACK output circuit stop condition detector start condition detector and ACK detector These circuits are used...

Page 578: ...register IICn base IICn control register IICCn base 2H IICn slave address register SVAn base 3H IICn clock select register IICCLn base 4H IICn function expansion register IICXn base 5H IICn status re...

Page 579: ...g is automatically cleared after being executed Its uses include cases in which a locally irrelevant extension code has been received The SCLn and SDAn lines are set to high impedance The STTn and SPT...

Page 580: ...s falling edge Master mode After output of nine clocks clock output is set to low level and wait is set Slave mode After input of nine clocks the clock is set to low level and wait is set for the mast...

Page 581: ...f the communication reservation function is disabled IICRSVn 1 The IICFn STCFn bit is set This trigger does not generate a start condition In the wait state when master device A restart condition is g...

Page 582: ...set only when the ACKEn bit has been set to 0 and during the wait period after the slave has been notified of final reception For master transmission A stop condition cannot be generated normally duri...

Page 583: ...et When a start condition is generated ALDn Arbitration loss detection 0 This status means either that there was no arbitration or that the arbitration result was a win 1 This status indicates the arb...

Page 584: ...e falling edge of the first byte s ninth clock Condition for clearing TRCn 0 Condition for setting TRCn 1 When a stop condition is detected Cleared by LRELn 1 communication save When the IICEn bit cha...

Page 585: ...ation save When the IICEn bit changes from 1 to 0 operation stop After reset When a start condition is detected SPDn Stop condition detection 0 Stop condition was not detected 1 Stop condition was det...

Page 586: ...t condition cannot be issued STTn bit cleared Condition for clearing STCFn 0 Condition for setting STCFn 1 Cleared by IICCn STTn 1 After reset When start condition is not issued and STTn flag is clear...

Page 587: ...d Therefore to issue the first start condition STTn 1 it is necessary to confirm that the bus has been released so as to not disturb other communications 3 Write the IICRSVn bit only when operation is...

Page 588: ...Condition for clearing CLDn 0 Condition for setting CLDn 1 When the SCLn pin is at low level When the IICEn 0 operation stop After reset When the SCLn pin is at high level DADn Detection of SDAn pin...

Page 589: ...n clock select registers The OCKSn registers control the I2 Cn division clock Access This register can be read written in 8 bit or 1 bit units Address base 20H Initial Value 00H This register is clear...

Page 590: ...ollowing table Note The clock chosen as the input clock that means IICLKPS must lie in the range of 1 MHz to 10 MHz Following table lists set ups for some useful I2C transfer clocks Note The calculati...

Page 591: ...its until the SCLn level exceeds the valid high level threshold VthH Then it does not pull SCLn to low level before the nominal high level time tSCLH_nom has elapsed This mechanism is the same used wh...

Page 592: ...ead written in 8 bit units Data should not be written to the IICn register during a data transfer Address base Initial Value 00H This register is cleared by any reset 9 SVAn IICn slave address registe...

Page 593: ...er and slave devices Input is Schmitt input Since outputs from the serial clock line and the serial data bus line are N ch open drain outputs an external pull up resistor is required Figure 18 4 Pin c...

Page 594: ...18 6 1 Start condition A start condition is met when the SCLn pin is high level and the SDAn pin changes from high level to low level The start condition for the SCLn and SDAn pins is a signal that t...

Page 595: ...the values of the SVAn register the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition Figure 18 7 Address Note The...

Page 596: ...e final data to be transmitted The transmitting device detects whether or not an ACK signal is returned after it transmits 8 bits of data When an ACK signal is returned the reception is judged as norm...

Page 597: ...ACK signal is automatically output in synchronization with the falling edge of the SCLn pin s eighth clock regardless of the value of the ACKEn bit No ACK signal is output if the received address is...

Page 598: ...serial transfer has been completed When used as the slave device the start condition can be detected Figure 18 10 Stop condition A stop condition is generated when the IICCn SPTn bit is set to 1 When...

Page 599: ...can begin 1 When master device has a nine clock wait and slave device has an eight clock wait master transmission slave reception and IICCn ACKEn bit 1 Figure 18 11 Wait signal 1 2 SCLn 6 SDAn 7 8 9...

Page 600: ...ing side writes data to the IICn register to cancel the wait status The master device can also cancel its own wait status via either of the following methods By setting the IICCn STTn bit to 1 By sett...

Page 601: ...to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn register 10XXX110B 2 IICSn register 10XXX000B 3 IICSn register 10XXX000B WTIMn bit 1 4 IICSn register 10XXXX00B 5 IICSn register 00000001B Remarks 1 Always ge...

Page 602: ...n bit 0 5 IICSn register 10XXX000B WTIMn bit 1 6 IICSn register 10XXXX00B 7 IICSn register 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 X don t care 2 n 0 to 2 2 When WTIMn bit...

Page 603: ...00B WTIMn bit 1 4 IICSn register 1010XX00B 5 IICSn register 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 X don t care 2 n 0 to 2 2 When WTIMn bit 1 SPTn bit 1 ST AD6 to AD0 RW...

Page 604: ...IICSn register 0001X000B 4 IICSn register 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 X don t care 2 n 0 to 2 2 When WTIMn bit 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP...

Page 605: ...gister 0001X000B 5 IICSn register 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 X don t care 2 n 0 to 2 2 When WTIMn bit 1 after restart address match ST AD6 to AD0 RW AK D7 to...

Page 606: ...5 IICSn register 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 X don t care 2 n 0 to 2 2 When WTIMn bit 1 after restart extension code reception ST AD6 to AD0 RW AK D7 to D0 AK...

Page 607: ...gister 00000X10B 4 IICSn register 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 X don t care 2 n 0 to 2 2 When WTIMn bit 1 after restart address mismatch not extension code ST A...

Page 608: ...ICSn register 0010X000B 4 IICSn register 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 X don t care 2 n 0 to 2 2 When WTIMn bit 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP...

Page 609: ...5 IICSn register 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 X don t care 2 n 0 to 2 2 When WTIMn bit 1 after restart address match ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to...

Page 610: ...r 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 X don t care 2 n 0 to 2 2 When WTIMn bit 1 after restart extension code reception ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 R...

Page 611: ...4 IICSn register 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 X don t care 2 n 0 to 2 2 When WTIMn bit 1 after restart address mismatch not extension code ST AD6 to AD0 RW AK...

Page 612: ...D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn register 0101X110B Example When ALDn bit is read during interrupt servicing 2 IICSn register 0001X000B 3 IICSn register 0001X000B 4 IICSn register 00000001B Remark...

Page 613: ...ter 0010X000B 4 IICSn register 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 X don t care 2 n 0 to 2 2 When WTIMn bit 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5...

Page 614: ...egister 01000110B Example When ALDn bit is read during interrupt servicing 2 IICSn register 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 2 n 0 to 2 ST AD6 to AD0 RW AK D7 to D0...

Page 615: ...read during interrupt servicing 3 IICSn register 00000001B Remarks 1 Always generated Generated only when SPIEn bit 1 2 n 0 to 2 2 When WTIMn bit 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2...

Page 616: ...ays generated Generated only when SPIEn bit 1 X don t care 2 Dn D6 to D0 n 0 to 2 2 Extension code ST AD6 to AD0 RW AK D7 to Dn ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 1 IICSn register 1000X110B 2 II...

Page 617: ...D0 AK SP 1 2 3 4 1 IICSn register 1000X110B 2 IICSn register 1000XX00B 3 IICSn register 01000100B Example When ALDn bit is read during interrupt servicing 4 IICSn register 00000001B Remarks 1 Always g...

Page 618: ...1 SPTn bit 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn register 1000X110B 2 IICSn register 1000XX00B 3 IICSn register 01000000B Example When ALDn bit is read during in...

Page 619: ...received neither the INTIICn signal nor a wait occurs 3 The numbers in the table indicate the number of the serial clock s clock signals Interrupt requests and wait control are both synchronized with...

Page 620: ...lect a particular slave device by transmitting the corresponding slave address Address match detection is performed automatically by hardware The INTIICn signal occurs when a local address has been se...

Page 621: ...lling edge of the eighth clock Higher four bits of data match EXCn bit 1 Seven bits of data match IICSn COIn bit 1 Since the processing after the interrupt request signal occurs differs according to t...

Page 622: ...CSn ALDn bit is set to 1 via the timing by which the arbitration loss occurred and the SCLn and SDAn lines are both set to high impedance which releases the bus Arbitration loss is detected based on t...

Page 623: ...set regardless of the wakeup function and this determines whether interrupt request signals are enabled or disabled Table 18 6 Status during arbitration and interrupt request signal generation timing...

Page 624: ...n register 2 Set the IICCn IICEn bit 3 Set the IICCn SPTn bit 2 When IICFn STCENn bit 1 Immediately after I2C0n operation is enabled the bus released status IICBSYn bit 0 is recognized regardless of t...

Page 625: ...reception Yes stop condition detection Wait Wait time is secured by software see Table 17 6 Yes start condition generation Communication reservation Start IICn write transfer Stop condition detection...

Page 626: ...reception ACKEn 0 SPTn 1 Generate stop condition No Yes Yes transmit INTIICn 1 No Yes Yes INTIICn 1 No Yes INTIICn 1 No Yes ACKDn 1 No Yes No ACKDn 1 TRCn 1 STCFn 0 End Transfer clock selection IICFn...

Page 627: ...r processing can be performed by transmitting these flags to the main processing instead of INTIICn signal 1 Communication mode flag This flag indicates the following communication statuses Clear mode...

Page 628: ...ag and ready flag the processing of the stop condition and start condition is performed by interrupts conditions are confirmed by flags For transmission repeat the transmission operation until the mas...

Page 629: ...Yes No No No No No No No No START Communication mode Communication mode Communication mode Ready Ready Read data Clear ready flag Clear ready flag Communication direction flag 1 WTIMn 1 WRELn 1 ACKEn...

Page 630: ...terrupt the ready flag is cleared 3 For data transmission reception when the ready flag is set operation returns from the interrupt while the IIC0n bus remains in the wait status Note 1 to 3 in the ab...

Page 631: ...IICSn TRCn bit which specifies the data transfer direction and then starts serial communication with the slave device The shift operation of the IICn register is synchronized with the falling edge of...

Page 632: ...n IICn ACKDn STDn SPDn WTIMn H H L L L L H H H L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCL0n SDA0n Processing by master device...

Page 633: ...Cn ACKDn STDn SPDn WTIMn H H L L L L L L H H H H L L L L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCL0n SDA0n Processing by master...

Page 634: ...SPDn WTIMn H H L L L L H H H L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCL0n SDA0n Processing by master device Transfer lines Proc...

Page 635: ...ICn or set WRELn IICn ACKDn STDn SPDn WTIMn H H L L H H L ACKEn MSTSn STTn L L SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCL0n SDA0n Processing by mas...

Page 636: ...CKDn STDn SPDn WTIMn H H H L L L L L L H H H L L L L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCL0n SDA0n Processing by master dev...

Page 637: ...t WRELn IICn ACKDn STDn SPDn WTIMn H H L L L H ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCL0n SDA0n Processing by master device Tran...

Page 638: ...638 Chapter 18 I2 C Bus IIC Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 639: ...lowing number of channels of the CAN controller Note 1 Throughout this chapter the individual CAN channels are identified by n for example CANn or CnGMCTRL for the CANn global control register 2 Throu...

Page 640: ...be controlled by CAN module bit rate prescaler register CnBRP and bit rate register CnBTR As an example the following sample point configurations can be configured 66 7 70 0 75 0 80 0 81 3 85 0 87 5 B...

Page 641: ...history list function Message transmission Unique ID can be set to each message buffer Transmit completion interrupt for each message buffer Message buffer number 0 to 7 specified as the transmit mess...

Page 642: ...dule CAN protocol layer This functional block is involved in the operation of the CAN protocol and its related settings CAN RAM This is the CAN memory functional block which is used to store message I...

Page 643: ...d format frame The standard format frame uses 11 bit identifiers which means that it can handle up to 2 048 messages 2 Extended format frame The extended format frame uses 29 bit 11 bits 18 bits ident...

Page 644: ...s value becomes dominant level 19 2 3 Data frame and remote frame 1 Data frame A data frame is composed of seven fields Figure 19 3 Data frame Note D Dominant 0 R Recessive 1 Frame Type Description Da...

Page 645: ...or remote frame Figure 19 5 Start of frame SOF Note D Dominant 0 R Recessive 1 If dominant level is detected in the bus idle state the start of frame is recognized If recessive level is detected at th...

Page 646: ...ransmitted MSB first Note D Dominant 0 R Recessive 1 Figure 19 7 Arbitration field in extended format mode Caution 1 ID28 to ID18 are identifiers 2 An identifier is transmitted MSB first Note D Domina...

Page 647: ...the remote frame there is no data field even if the data length code is not 0000B Frame Type RTR Bit Data frame 0 D Remote frame 1 R Frame Format SRR Bit IDE Bit Number of Bits Standard format mode No...

Page 648: ...ressed as follows P X X15 X14 X10 X8 X7 X4 X3 1 Transmitting node Transmits the CRC sequence calculated from the data before bit stuffing in the start of frame arbitration field control field and data...

Page 649: ...ets the ACK slot to the dominant level The transmitting node outputs two recessive level bits 7 End of frame EOF The end of frame field indicates the end of data frame remote frame Figure 19 12 End of...

Page 650: ...rame space consists of an intermission field a suspend transmission field and a bus idle field Figure 19 14 Interframe space error passive node Note 1 Bus idle State in which the bus is not used by an...

Page 651: ...status Table 19 6 Operation in error status Error Status Operation Error active A node in this status can transmit immediately after a 3 bit intermission Error passive A node in this status can transm...

Page 652: ...level is detected 6 bits in a row 2 Error flag 2 0 to 6 Nodes receiving error flag 1 detect bit stuff errors and issues this error flag 3 Error delimiter 8 Outputs 8 recessive level bits consecutively...

Page 653: ...1 R D 2 3 6 bits 0 to 6 bits 8 bits 4 5 Interframe space or overload frame Overload delimiter Overload flag node n Overload flag node m Frame Overload frame No Name Bit count Definition 1 Overload fla...

Page 654: ...tion field carries a dominant level Caution If the extended format data frame and the standard format remote frame conflict on the bus if ID28 to ID18 of both of them are the same the standard format...

Page 655: ...types Type Description of error Detection state Detection method Detection condition Transmission Reception Field Frame Bit error Comparison of the output level and level on the bus except stuff bit M...

Page 656: ...1 In this case the bus state must be tested because it is considered that the bus has a serious fault An error counter value of 128 or more indicates an error passive state and the TECS1 or RECS1 bit...

Page 657: ...7 TECS1 TECS0 01 Reception 96 to 127 RECS1 RECS0 01 Error passive Transmission 128 to 255 TECS1 TECS0 11 Outputs a passive error flag 6 consecutive recessive level bits on detection of the error Trans...

Page 658: ...g output 2 A stuff error is detected in an arbitration field that transmitted a recessive level as a stuff bit but a dominant level is detected 8 No change Bit error detection while active error flag...

Page 659: ...d message buffer using application software or stopping the operation of the CAN module can be performed by clearing the CnGMCTRL GOM bit to 0 Next the module requests to change the mode from the init...

Page 660: ...annot enter the initialization mode In this case release the module from the CAN sleep or stop mode and then make a request to place the module in the initialization mode Figure 19 17 Recovery from bu...

Page 661: ...o the CAN bus after it has monitored 11 consecutive recessive level bits For details refer to the processing in Figure 19 51 on page 762 Caution This function is not defined by the CAN protocol ISO 11...

Page 662: ...e segment 2 is equivalent to phase segment 2 Figure 19 18 Segment setting Table 19 15 Segment setting Note 1 IPT Information Processing Time 2 Reference The CAN protocol specification defines the segm...

Page 663: ...e length of this segment is set so that ACK is returned before the start of phase segment 1 Time of prop segment Delay of output buffer 2 Delay of CAN bus Delay of input buffer This segment compensate...

Page 664: ...tion Synchronization is established again if a level change is detected on the bus during reception only if a recessive level was sampled previously The phase error of the edge is given by the relativ...

Page 665: ...n external transceiver Figure 19 22 Connection to CAN bus CAN bus Bit timing CAN bus Bit timing Phase segment 1 Prop segment Sync segment Phase segment 2 Phase segment 1 Prop segment Sync segment Phas...

Page 666: ...following tables are offsets to the programmable peripheral area base address PBA The recommended setting of PBA is 8FFBH This setting would define the programmable peripheral area base address PBA 03...

Page 667: ...caler register CnBRP CANn module bit rate register CnBTR CANn module last in pointer register CnLIPT CANn module receive history list register CnRGPT CANn module last out pointer register CnLOPT CANn...

Page 668: ...ndefined 048H CAN0 module mask 3 register C0MASK3L Undefined 04AH C0MASK3H Undefined 04CH CAN0 module mask 4 register C0MASK4L Undefined 04EH C0MASK4H Undefined 050H CAN0 module control register C0CTR...

Page 669: ...d mx20H 2H CAN0 message data byte 23 register m C0MDATA23m Undefined mx20H 2H CAN0 message data byte 2 register m C0MDATA2m Undefined mx20H 3H CAN0 message data byte 3 register m C0MDATA3m Undefined m...

Page 670: ...H CAN1 module mask 3 register C1MASK3L Undefined 04AH C1MASK3H Undefined 04CH CAN1 module mask 4 register C1MASK4L Undefined 04EH C1MASK4H Undefined 050H CAN1 module control register C1CTRL 0000H 052H...

Page 671: ...ned mx20H 2H CAN1 message data byte 23 register m C1MDATA23m Undefined mx20H 2H CAN1 message data byte 2 register m C1MDATA2m Undefined mx20H 3H CAN1 message data byte 3 register m C1MDATA3m Undefined...

Page 672: ...dress offseta Symbol Bit 7 15 Bit 6 14 Bit 5 13 Bit 4 12 Bit 3 11 Bit 2 10 Bit 1 9 Bit 0 8 40H CnMASK1L CMID7 to CMID0 41H CMID15 to CMID8 42H CnMASK1H CMID23 to CMID16 43H 0 0 0 CMID28 to CMID24 44H...

Page 673: ...PRS7 to TQPRS0 5CH CnBTR 0 0 0 0 TSEG13 to TSEG10 5DH 0 0 SJW1 SJW0 0 TSEG22 to TSEG20 5EH CnLIPT LIPT7 to LIPT0 60H CnRGPT W 0 0 0 0 0 0 0 Clear ROVF 61H 0 0 0 0 0 0 0 0 60H CnRGPT R 0 0 0 0 0 0 RHPM...

Page 674: ...data byte 2 3H CnMDATA3m Message data byte 3 4H CnMDATA45m Message data byte 4 5H Message data byte 5 4H CnMDATA4m Message data byte 4 5H CnMDATA5m Message data byte 5 6H CnMDATA67m Message data byte...

Page 675: ...it does not change and access to the message buffer registers or registers related to transmit history or receive history remains disabled Note MBON bit is cleared to 0 when the CAN module enters CAN...

Page 676: ...tion The GOM bit is cleared only in the initialization mode b Write EFSD Bit enabling forced shut down 0 Forced shut down by GOM bit 0 disabled 1 Forced shut down by GOM bit 0 enabled GOM Global opera...

Page 677: ...02H 7 6 5 4 3 2 1 0 CnGMCS 0 0 0 0 CCP3 CCP2 CCP1 CCP0 CCP3 CCP2 CCP1 CCP1 CAN module system clock fCANMOD 0 0 0 0 fCAN 1 0 0 0 1 fCAN 2 0 0 1 0 fCAN 3 0 0 1 1 fCAN 4 0 1 0 0 fCAN 5 0 1 0 1 fCAN 6 0 1...

Page 678: ...ted clearing processing is complete Caution Do not set the ABTTRG bit in the initialization mode If the ABTTRG bit is set in the initialization mode the operation is not guaranteed after the CAN modul...

Page 679: ...ine clear request bit 0 The automatic block transmission engine is in idle status or under operation 1 Request to clear the automatic block transmission engine After the automatic block transmission e...

Page 680: ...transmitted onto the CAN bus differs depending on the status of transmission from the other station or how a request to transmit a message other than an ABT message message buffers 8 to 31 is made Af...

Page 681: ...10 9 8 CnMASK1L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 CnMASK1H 0 0 0 CMID28 CMID27 CMID26 CMID25 C...

Page 682: ...12 11 10 9 8 CnMASK3H 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 After reset Undefined R W Address CnMASK4L CnRBaseAddr 04CH CnMA...

Page 683: ...conditions timing The SOF bit of a transmit frame is detected The first bit of an error flag is detected during a transmit frame 2 The TSTAT bit is cleared to 0 under the following conditions timing D...

Page 684: ...ing a message frame in the normal mode and the other in the reception mode the VALID bit is not set to 1 before the transmitting node enters the error passive status 4 The VALID bit is read only in th...

Page 685: ...ion normal operation mode with ABT 0 1 1 Receive only mode 1 0 0 Single shot mode 1 0 1 Self test mode Other than above Setting prohibited 15 14 13 12 11 10 9 8 CnCTRL Set CCERC Set AL 0 Set PSMODE 1...

Page 686: ...ve PSMODE1 bit is not changed Set OPMODE0 Clear OPMODE0 Setting of OPMODE0 bit 0 1 OPMODE0 bit is cleared to 0 1 0 OPMODE0 bit is set to 1 Other than above OPMODE0 bit is not changed Set OPMODE1 Clear...

Page 687: ...Address CnLEC CnRBaseAddr 052H 7 6 5 4 3 2 1 0 CnLEC 0 0 0 0 0 LEC2 LEC1 LEC0 LEC2 LEC1 LEC0 Last CAN protocol error information 0 0 0 No error 0 0 1 Stuff error 0 1 0 Form error 0 1 1 ACK error 1 0...

Page 688: ...ission error counter status bit 0 0 The value of the transmission error counter is less than that of the warning level 96 0 1 The value of the transmission error counter is in the range of the warning...

Page 689: ...nERC REPS REC6 REC5 REC4 REC3 REC2 REC1 REC0 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REPS Reception error passive status bit 0 The value of the reception error counter is not error pas...

Page 690: ...interrupt corresponding to interrupt status register CINTSx is enabled 15 14 13 12 11 10 9 8 CnIE 0 0 Set CIE5 Set CIE4 Set CIE3 Set CIE2 Set CIE1 Set CIE0 7 6 5 4 3 2 1 0 0 0 Clear CIE5 Clear CIE4 C...

Page 691: ...n above CIE0 bit is not changed After reset 0000H R W Address CnINTS CnRBaseAddr 058H 15 14 13 12 11 10 9 8 CnINTS 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 CINTS5...

Page 692: ...set when the CAN sleep mode has been released by software b Write 15 14 13 12 11 10 9 8 CnINTS 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 Clear CINTS5 Clear CINTS4 Clear CINTS3 Clear CINTS2 Clear CINTS1 Cle...

Page 693: ...register is used to control the data bit time of the communication baud rate After reset FFH R W Address CnBRP CnRBaseAddr 05AH 7 6 5 4 3 2 1 0 CnBRP TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 T...

Page 694: ...bit time DBT Time segment 1 TSEG1 Phase segment 2 Phase segment 1 Sample point SPT Prop segment Sync segment Time segment 2 TSEG2 SJW1 SJW0 Length of synchronization jump width 0 0 1TQ 0 1 2TQ 1 0 3TQ...

Page 695: ...read value of the CnLIPT register is undefined TSEG13 TSEG12 TSEG11 TSEG10 Length of time segment 1 0 0 0 0 Setting prohibited 0 0 0 1 2TQNote 0 0 1 0 3TQNote 0 0 1 1 4TQ 0 1 0 0 5TQ 0 1 0 1 6TQ 0 1 1...

Page 696: ...ndicate the number of the message buffer in which a data frame or a remote frame has been stored RHPMNote 1 Receive history list pointer match 0 The receive history list has at least one message buffe...

Page 697: ...ead value of the CnLOPT register is undefined 15 14 13 12 11 10 9 8 CnRGPT 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Clear ROVF Clear ROVF Setting of ROVF bit 0 ROVF bit is not changed 1 ROVF bit...

Page 698: ...tents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last THPMNote 1 Transmit history pointer match 0 The transmit history list has at least one mess...

Page 699: ...troller CAN Chapter 19 Preliminary User s Manual U17566EE1V2UM00 Clear TOVF Setting of TOVF bit 0 TOVF bit is not changed 1 TOVF bit is cleared to 0 Downloaded from Elcodis com electronic components d...

Page 700: ...k function enable bit 0 Time stamp lock function stopped The TSOUT signal is toggled each time the selected time stamp capture event occurs 1 Time stamp lock function enabled The TSOUT output signal i...

Page 701: ...Other than above TSLOCK bit is not changed Set TSSEL Clear TSSEL Setting of TSSEL bit 0 1 TSSEL bit is cleared to 0 1 0 TSSEL bit is set to 1 Other than above TSSEL bit is not changed Set TSEN Clear T...

Page 702: ...TA01 1 MDATA01 0 7 6 5 4 3 2 1 0 CnMDATA0m MDATA0 7 MDATA0 6 MDATA0 5 MDATA0 4 MDATA0 3 MDATA0 2 MDATA0 1 MDATA0 0 7 6 5 4 3 2 1 0 CnMDATA1m MDATA1 7 MDATA1 6 MDATA1 5 MDATA1 4 MDATA1 3 MDATA1 2 MDATA...

Page 703: ...MDATA4 0 7 6 5 4 3 2 1 0 CnMDATA5m MDATA5 7 MDATA5 6 MDATA5 5 MDATA5 4 MDATA5 3 MDATA5 2 MDATA5 1 MDATA5 0 15 14 13 12 11 10 9 8 CnMDATA67m MDATA67 15 MDATA67 14 MDATA67 13 MDATA67 12 MDATA67 11 MDATA...

Page 704: ...68 7 6 5 4 3 2 1 0 CnMDLCm 0 0 0 0 MDLC3 MDLC2 MDLC1 MDLC0 MDLC3 MDLC2 MDLC1 MDLC0 Data length of transmit receive message 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 byte...

Page 705: ...to 0 Even if a remote frame whose ID matches has been received from the CAN bus with the RTR bit of the transmit message buffer set to 1 to transmit a remote frame that remote frame is not received o...

Page 706: ...er reset Undefined R W Address refer to CAN registers overview on page 668 15 14 13 12 11 10 9 8 CnMIDLm ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 15 14 13...

Page 707: ...fer overwrite status bit 0 The message buffer is not overwritten by a newly received data frame 1 The message buffer is overwritten by a newly received data frame IE Message buffer interrupt request e...

Page 708: ...10 9 8 CnMCTRLm 0 0 0 0 Set IE 0 Set TRQ Set RDY 7 6 5 4 3 2 1 0 0 0 0 Clear MOW Clear IE Clear DN Clear TRQ Clear RDY Clear MOW Setting of MOW bit 0 MOW bit is not changed 1 MOW bit is cleared to 0 S...

Page 709: ...nIE CANn module interrupt status register CnINTS CANn module receive history list register CnRGPT CANn module transmit history list register CnTGPT CANn module time stamp register CnTS CANn message co...

Page 710: ...0 0 1 1 clear 1 1 0 1 1 0 0 0 Set No change Clear Bit status Register s current value Write value Register s value after write operation Clear Clear No change No change Set 15 14 13 12 11 10 9 8 7 6...

Page 711: ...ge buffer while a message is being received or transmitted without affecting other transmission reception operations 1 To redefine message buffer in initialization mode Place the CAN module in the ini...

Page 712: ...buffer following redefinition are those stored after the message buffer has been redefined If no ID and IDE are stored after redefinition redefine the message buffer again 2 When a message is transmi...

Page 713: ...bit in the interframe space the values of the OPMODE2 to OPMODE0 bits are changed to 00H After issuing a request to change the mode to the initialization mode read the OPMODE2 to OPMODE0 bits until th...

Page 714: ...ady for reception CnMCTRLm RDY bit is set to 1 When two or more message buffers of the CAN module receive a message the message is stored according to the priority explained below The message is alway...

Page 715: ...frame will be recorded chronologically The RGPT pointer is utilized as a read pointer that reads a recorded message buffer number from the RHL This pointer indicates the first RHL element that the CP...

Page 716: ...ter RGPT Receive history list RHL Message buffer 1 Message buffer 5 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 7 Message buffer 2 Message buffer 9 Message buffer 9 Receive histo...

Page 717: ...ample let us assume that all messages that have a standard format ID in which bits ID27 to ID25 are 0 and bits ID24 and ID22 are 1 are to be stored in message buffer 14 The procedure for this example...

Page 718: ...o CMID24 and CMID22 bits are cleared to 0 and the CMID28 CMID23 and CMID21 to CMID0 bits are set to 1 CMID2 8 CMID2 7 CMID2 6 CMID2 5 CMID2 4 CMID2 3 CMID2 2 CMID2 1 CMID2 0 CMID1 9 CMID1 8 1 0 0 0 0...

Page 719: ...d the IE bit in message buffer k 1 is set to 1 interrupts enabled In this case a reception completion interrupt occurs when a message has been received and stored in message buffer k 1 indicating that...

Page 720: ...MDLCm DLC0 bits store the received DLC value The CnMDATA0m to CnMDATA7m registers in the data area are not updated data before reception is saved The CnMCTRLm DN bit is set to 1 The CnINTS CINTS1 bit...

Page 721: ...rity control Transmission priority is controlled by the identifier ID Figure 19 29 Message processing example After the transmit message search the transmit message with the highest priority of the tr...

Page 722: ...gnal INTRRX1 is output if the CnIE CIE0 bit is set to 1 and if the interrupt enable bit IE of the corresponding transmit message buffer is set to 1 Priority Conditions Description 1 high Value of firs...

Page 723: ...tored a frame will be recorded chronologically The TGPT pointer is utilized as a read pointer that reads a recorded message buffer number from the THL This pointer indicates the first THL element that...

Page 724: ...ge buffer 2 Message buffer 9 When message buffer 6 is read If transmission from message buffers 3 and 4 is completed Last out message pointer LOPT Transmit history list get pointer TGPT Transmit histo...

Page 725: ...uccessively A delay time can be inserted by program in the interval in which the transmission request TRQ bit is automatically set while successive transmission is being executed The delay time to be...

Page 726: ...ime that is inserted in the period from completion of the preceding ABT message to setting of the TRQ bit for the next ABT message when the transmission requests are set in the order of message number...

Page 727: ...is requested the internal ABT pointer points to the last transmitted message buffer for details refer to the process in Figure 19 44 on page 755 When the normal operation mode with ABT is resumed aft...

Page 728: ...p mode is held pending iii No transmission request is pending If any one of the conditions mentioned above is not met the CAN module will operate as follows If the CAN sleep mode is requested from the...

Page 729: ...s The CANn module registers can be read except for the CnLIPT CnRGPT CnLOPT and CnTGPT registers The CANn message buffer registers cannot be written or read A request for transition to the initializat...

Page 730: ...equest the CAN stop mode If a bus change occurs at the CAN reception pin CRXDn while this process is being performed the CAN sleep mode is automatically released In this case the CAN stop mode transit...

Page 731: ...saving mode and return to normal operation mode To further reduce the power consumption of the CPU the internal clocks including that of the CAN module may be stopped In this case the operating clock...

Page 732: ...the transmission reception error counter is at the warning level or in the error passive or bus off state 2 This interrupt is generated when a stuff error form error ACK error bit error or CRC error...

Page 733: ...sage frame has been received in the CAN protocol layer without occurrence of an error and with an appropriate ACK between nodes connected to the CAN bus A valid reception does not require message fram...

Page 734: ...ot mode In the single shot mode automatic re transmission as defined in the CAN protocol is switched off According to the CAN protocol a message frame transmission that has been aborted by either arbi...

Page 735: ...nally looped back The CAN transmission pin CTXDn is fixed to the recessive level If the falling edge on the CAN reception pin CRXDn is detected after the CAN module has entered the CAN sleep mode from...

Page 736: ...bus by reading the captured value The TSOUT signal can be selected from the following two event sources and is specified by the CnTS TSSEL bit SOF event start of frame TSSEL bit 0 EOF event last bit o...

Page 737: ...eration mode with ABT because message buffer 0 must be set as a transmit message buffer In this operation mode therefore the function to stop toggle of the TSOUT signal by the TSLOCK bit cannot be use...

Page 738: ...6 1110 101 72 7 22 1 11 5 5 1111 100 77 3 21 1 4 8 8 1011 111 61 9 21 1 6 7 7 1100 110 66 7 21 1 8 6 6 1101 101 71 4 21 1 10 5 5 1110 100 76 2 21 1 12 4 4 1111 011 81 0 20 1 3 8 8 1010 111 60 0 20 1 5...

Page 739: ...010 80 0 15 1 10 2 2 1011 001 86 7 15 1 12 1 1 1100 000 93 3 14 1 1 6 6 0110 101 57 1 14 1 3 5 5 0111 100 64 3 14 1 5 4 4 1000 011 71 4 14 1 7 3 3 1001 010 78 6 14 1 9 2 2 1010 001 85 7 14 1 11 1 1 1...

Page 740: ...1 001 81 8 11 1 8 1 1 1000 000 90 9 10 1 1 4 4 0100 011 60 0 10 1 3 3 3 0101 010 70 0 10 1 5 2 2 0110 001 80 0 10 1 7 1 1 0111 000 90 0 9 1 2 3 3 0100 010 66 7 9 1 4 2 2 0101 001 77 8 9 1 6 1 1 0110 0...

Page 741: ...001 87 5 500 1 00000000 16 1 13 1 1 1101 000 93 8 500 2 00000001 8 1 1 3 3 0011 010 62 5 500 2 00000001 8 1 3 2 2 0100 001 75 0 500 2 00000001 8 1 5 1 1 0101 000 87 5 250 2 00000001 16 1 1 7 7 0111 11...

Page 742: ...3 3 12 00001011 8 1 5 1 1 0101 000 87 5 33 3 10 00001001 24 1 7 8 8 1110 111 66 7 33 3 10 00001001 24 1 9 7 7 1111 110 70 8 33 3 12 00001011 20 1 7 6 6 1100 101 70 0 33 3 12 00001011 20 1 9 5 5 1101 1...

Page 743: ...8 8 500 2 00000001 16 1 7 4 4 1010 011 75 0 500 2 00000001 16 1 9 3 3 1011 010 81 3 500 2 00000001 16 1 11 2 2 1100 001 87 5 500 2 00000001 16 1 13 1 1 1101 000 93 8 500 4 00000011 8 1 3 2 2 0100 001...

Page 744: ...0 1 9 5 5 1101 100 75 0 33 3 24 00010111 20 1 11 4 4 1110 011 80 0 33 3 30 00011101 16 1 7 4 4 1010 011 75 0 33 3 30 00011101 16 1 9 3 3 1011 010 81 3 33 3 32 00011111 15 1 8 3 3 1010 010 80 0 33 3 32...

Page 745: ...operation mode normal operation mode with ABT receive only mode single shot mode self test mode START Set CnGMCS register Set CnBRP register CnBTR register Set CnIE register Set CnMASK register Initia...

Page 746: ...access registers other than the CnCTRL and CnGMCTRL registers e g set a message buffer Note OPMODE Normal operation mode normal operation mode with ABT receive only mode single shot mode self test mo...

Page 747: ...he application Clear the CnMCTRLm RDY CnMCTRLm TRQ and CnMCTRLm DN bits to 0 Clear the CnMCONFm MA0 bit to 0 START Set CnMCONFm register Set CnMIDHm register CnMIDLm register Set CnMDLCm register Clea...

Page 748: ...NFm MT2 to CnMCONFm MT0 bits 001B to 101B Figure 19 37 Message buffer redefinition START Clear RDY bit Set RDY bit 0 Clear RDY bit 1 Set message buffers Set RDY bit Set RDY bit 1 Clear RDY bit 0 END R...

Page 749: ...Q bit should not be set at the same time START Set TRQ bit Set TRQ bit 1 Clear TRQ bit 0 END TRQ bit 0 Yes No Clear RDY bit Set RDY bit 0 Clear RDY bit 1 Set RDY bit Set RDY bit 1 Clear RDY bit 0 RDY...

Page 750: ...with ABT can only be applied to message buffers 0 to 7 For message buffers other than the ABT message buffers see Figure 19 38 on page 749 Start END Clear RDY bit Set RDY bit 0 Clear RDY bit 1 ABTTRG...

Page 751: ...rupt processing Read CnLOPT register Clear RDY bit Set RDY bit 0 Clear RDY bit 1 RDY bit 0 No Yes Set RDY bit Set RDY bit 1 Clear RDY bit 0 Set TRQ bit Set TRQ bit 1 Clear TRQ bit 0 Data frame or remo...

Page 752: ...r TOVF bit Clear TOVF bit 1 THPM bit 1 Yes No Yes No Transmit completion interrupt processing Set RDY bit Set RDY bit 1 Clear RDY bit 0 Set TRQ bit Set RDY bit 1 Clear RDY bit 0 Read CnTGPT register R...

Page 753: ...1 THPM bit 1 Yes No Yes No Yes No Clear CINTS0 bit Clear CINTS0 bit 1 Clear RDY bit Set RDY bit 0 Clear RDY bit 1 Set RDY bit Set RDY bit 1 Clear RDY bit 0 Set TRQ bit Set TRQ bit 1 Clear TRQ bit 0 R...

Page 754: ...e transition request confirm that there is no transmission request left using this processing 3 The TSTAT bit can be periodically checked by a user application START No Yes END Clear TRQ bit Set TRQ b...

Page 755: ...gress 2 Make a CAN sleep mode CAN stop mode transition request after the ABTTRG bit is cleared following the procedure shown in Figure 19 44 or Figure 19 45 When clearing a transmission request in an...

Page 756: ...ssing is in progress 2 Make a CAN sleep mode CAN stop mode request after the ABTTRG bit is cleared following the procedure shown in Figure 19 44 or Figure 19 45 When clearing a transmission request in...

Page 757: ...PT register Note Check the MUC and DN bits using one read access START END Read CnLIPT register DN bit 0 and MUC bit 0Note Yes No Clear DN bit Clear DN bit 1 Clear CINTS1 bit Clear CINTS1 bit 1 Transm...

Page 758: ...the MUC and DN bits using one read access END Read CnRGPT register DN bit 0 and MUC bit 0Note Yes No ROVF bit 1 Yes No Clear ROVF bit Clear ROVF bit 1 RHPM bit 1 Yes START No Clear DN bit Clear DN bit...

Page 759: ...sing one read access Start END Read CnRGPT register DN bit 0 and MUC bit 0Note Yes No ROVF bit 1 Yes No Clear ROVF bit Clear ROVF bit 1 Clear DN bit Clear DN bit 1 RHPM bit 1 No Yes CINTS1 bit 1 No Ye...

Page 760: ...ing according to Figure 19 43 on page 754 and Figure 19 44 on page 755 START when PSMODE 1 0 00B END Set PSMODE0 bit Set PSMODE0 bit 1 Clear PSMODE0 bit 0 No PSMODE0 bit 1 CAN sleep mode CAN stop mode...

Page 761: ...t Set PSMODE1 bit 0 Clear PSMODE1 bit 1 CAN stop mode CAN sleep mode Clear PSMODE0 bit Set PSMODE0 bit 0 Clear PSMODE0 bit 1 Clear CINTS5 bit Clear CINTS5 bit 1 Bus activity 0 PSMODE0 bit 0 CINTS5 bit...

Page 762: ...RC bit Set CCERC bit 1 Clear CCERC bit 0 INIT mode END Yes No Yes Set CnCTRL register clear OPMODE bit Access to register other than CnCTRL and CnGMCTRL registers Forced recovery from bus off Set CnCT...

Page 763: ...er s Manual U17566EE1V2UM00 Figure 19 52 Normal shutdown process START Clear GOM bit Set GOM bit 0 Clear GOM bit 1 Shutdown successful GOM bit 0 EFSD bit 0 END GOM bit 0 No Yes INIT mode Downloaded fr...

Page 764: ...ting the EFSD bit and clearing the GOM bit Note OPMODE Normal operation mode normal operation mode with ABT receive only mode single shot mode self test mode START Set EFSD bit Set EFSD bit 1 Clear GO...

Page 765: ...S3 bit 1 CINTS4 bit 1 Clear CINTS2 bit Clear CINTS2 bit 1 END Yes No No Yes No Yes Check CAN module state read CnINFO register Check CAN protocol error state read CnLEC register Clear CINTS3 bit Clear...

Page 766: ...ing CPU stand by from CAN sleep mode START END Set PSMODE0 bit Set PSMODE0 bit 1 Clear PSMODE0 bit 0 Yes No CINTS5 bit 1 PSMODE0 bit 1 MBON bit 0 No Yes Yes No Clear CINTS5 bit Clear CINTS5 bit 1 CAN...

Page 767: ...e START END Set PSMODE0 bit Set PSMODE0 bit 1 Clear PSMODE0 bit 0 PSMODE0 bit 1 MBON bit 0 Yes No PSMODE1 bit 1 No Yes CAN stop mode Yes No Set PSMODE1 bit Set PSMODE1 bit 1 Clear PSMODE1 bit 0 Clear...

Page 768: ...tion the registers of the CAN macro will not operate The worst case maximum length of this latency time is given by the CAN bus speed and the rule of the CAN bus about the frequency of recessive to do...

Page 769: ...e A D Converter converts analog input signals into digital values The A D Converter has the following features 10 bit resolution Successive approximation method The following functions are provided as...

Page 770: ...20 1 Block diagram of A D Converter ANI0 ANI1 ANI2 ANIn ADA0M0 ADA0M1 ADA0M2 ADA0S SAR ADCR00 ADCR01 ADCR0n AVREF AVDD ADA0CE bit ADA0CE bit AVSS ADA0CE bit INTTZ5UV SPCLK0 16 MHz Voltage comparator...

Page 771: ...rsion result register nH ADCR0Hn The ADCR0n register is a 16 bit register that stores the A D conversion result ADCR0n consist of 16 registers and the A D conversion result is stored in the 10 higher...

Page 772: ...alog input signal 7 ANIn pins These are analog input pins for the 16 A D Converter channels and are used to input analog signals to be converted into digital signals Pins other than the one selected a...

Page 773: ...that specifies the operation mode and controls conversion operations This register can be read orwritten in 8 bit or 1 bit units However bit 0 is read only Reset input clears this register to 00H Aft...

Page 774: ...ADA0M1 ADC mode register 1 The ADA0M1 register is an 8 bit register that controls the conversion time specification This register can be read or written in 8 bit or 1 bit units Reset input clears thi...

Page 775: ...sary stabilization time The stabilization time applies only prior to the first sampling 3 2 1 0 div conversion timeb b The conversion time is calculated by 31 x div fSPCLK0 sampling timec c The sampli...

Page 776: ...read or written in 8 bit or 1 bit units Reset input clears this register to 00H Caution Be sure to clear bits 7 to 1 After reset 00H R W Address FFFFF203H 7 6 5 4 3 2 1 0 ADA0M2 0 0 0 0 0 0 ADA0TMD 1...

Page 777: ...A0S1 ADA0S0 ADA0S4 ADA0S3 ADA0S2 ADA0S1 ADA0S0 Select mode Scan mode 0 0 0 0 0 ANI0 ANI0 0 0 0 0 1 ANI1 ANI0 ANI1 0 0 0 1 0 ANI2 ANI0 to ANI2 0 0 0 1 1 ANI3 ANI0 to ANI3 0 0 1 0 0 ANI4 ANI0 to ANI4 0...

Page 778: ...CR01 FFFFF212H ADCR02 FFFFF214H ADCR03 FFFFF216H ADCR04 FFFFF218H ADCR05 FFFFF21AH ADCR06 FFFFF21CH ADCR07 FFFFF21EH ADCR08 FFFFF220H ADCR09 FFFFF222H ADCR010 FFFFF224H ADCR011 FFFFF226H ADCR012 FFFFF...

Page 779: ...ersion result register n ADCR0n Figure 20 2 shows the relationship between the analog input voltage and the A D conversion results Figure 20 2 Relationship between analog input voltage and A D convers...

Page 780: ...to Power fail compare mode on page 785 7 ADA0PFT ADC power fail compare threshold value register The ADA0PFT register sets the compare value in the power fail compare mode This register can be read or...

Page 781: ...ed by the voltage comparator If the analog input voltage is higher than 1 2 AVREF the MSB of the SAR register remains set If it is lower than 1 2 AVREF the MSB is reset 6 Next bit 8 of the SAR registe...

Page 782: ...is started the ADA0EF bit is set to 1 indicating that conversion is in progress If the ADA0M0 ADA0M2 ADA0S ADA0PFM or ADA0PFT register is written during conversion the conversion is aborted and start...

Page 783: ...unless the ADA0CE bit of the ADA0M0 register is cleared to 0 Figure 20 4 Timing example of continuous select mode operation ADA0S 01H 2 Continuous scan mode In this mode analog input pins are sequenti...

Page 784: ...6 ANI1 Data 7 ANI2 Data 1 ANI0 Data 2 ANI1 Data 3 ANI2 Data 4 ANI3 Data 5 ANI0 Data 6 ANI1 ADCR0n INTAD Conversion start Set ADA0CE bit 1 ANI3 ANI0 ANI1 ANI2 Data 1 Data 2 Data 3 Data 4 Data 6 Data 5...

Page 785: ...alue of the ADA0PFT register when conversion is completed and the INTAD signal is generated only if ADCR0H0 ADA0PFT In the power fail compare mode two modes are available as modes in which to set the...

Page 786: ...wer fail comparison is performed only on ANI0 After each conversion of ANI0 the higher 8 bits of conversion result in ADA0CR0H0 is compared with the value of the ADA0PFT register If the result of powe...

Page 787: ...a Timing example b Block diagram A D converter ADCR0n registers Analog input pin ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI15 ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR015 ADCR0n A D conversion ANI3 INTAD...

Page 788: ...ource becomes higher To lower the noise connecting an external capacitor as shown in Figure 20 8 is recommended Figure 20 8 Processing of analog input pin 4 Alternate I O The analog input pins ANIn fu...

Page 789: ...f the newly selected analog input pin has not been completed When A D conversion is stopped clear the ADIF flag before resuming conversion Figure 20 9 Generation timing of A D conversion end interrupt...

Page 790: ...of the resolution 1 FSR Maximum value of convertible analog input voltage Minimum value of convertible analog input voltage 100 AVREF 0 100 AVREF 100 When the resolution is 10 bits 1 LSB is as follows...

Page 791: ...error full scale error integral linearity error or differential linearity error in the characteristics table Figure 20 11 Quantization error 4 Zero scale error This is the difference between the actua...

Page 792: ...linearity error Ideally the width to output a specific code is 1 LSB This error indicates the difference between the actually measured value and its theoretical value when a specific code is output F...

Page 793: ...le error are 0 Figure 20 15 Integral linearity error 8 Conversion time This is the time required to obtain a digital output after an analog input voltage has been assigned The conversion time in the c...

Page 794: ...794 Chapter 20 A D Converter ADC Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 795: ...ulse width of 8 bits precision 1 bit addition function enables an average pulse width precision of 1 2 bit resulting in a pseudo 9 bit precision PWM frequency up to 32 KHz automatic PWM phase shift fo...

Page 796: ...bit addition is enabled and it routes the output signals to the corresponding output pins SMk1 to SMk4 Figure 21 1 Stepper Motor Controller Driver 0 block diagram SM11 sin1 8 bit compare register MCPM...

Page 797: ...re register MCPMn60 8 bit compare register MCPMn61 1 bit add circuit 1 bit add circuit 1 bit add circuit 8 bit free running counter CNT1 Output Control Output Control Output Control SM52 sin5 SM53 cos...

Page 798: ...H Compare registers MCMPnk0 k 1 to 6 base 2H 4H 6H 8H 16H 18H MCMPnk1 k 1 to 6 base 3H 5H 7H 9H 17H 19H MCMPnkHW k 1 to 6 base 2H 4H 6H 8H 16H 18H Compare control registers MCMPCnk k 1 to 6 base AH CH...

Page 799: ...TCn0 In register MCNTCn1 this bit is set to 0 Stepper Motor Controller Driver control 0 Stepper Motor Controller Driver operation is disabled 1 Stepper Motor Controller Driver operation is enabled Thi...

Page 800: ...efine the PWM pulse width for the sine side of the connected meters The contents of the registers are continuously compared to the timer counter value Registers MCMP10 to MCMP40 are compared to CNT0 R...

Page 801: ...responding bit MCMPCnk TEN 0 2 Don t write to the compare register MCMPnk1 until the corresponding bit MCMPCnk TEN has been reset to 0 automatically 3 To enable master to slave register copy upon next...

Page 802: ...k0 MCMPnk1 master to slave register copy is disabled New data can be written to compare registers MCMPnk0 or MCMPnk1 1 MCMPnk0 MCMPnk1 master to slave register copy is enabled The copy process will ta...

Page 803: ...positive cos cosine side negative cos Two output control circuits select which signal sign for sine side and cosine side is output bits MCMPCnk DIR 1 0 At the remaining two output pins the signal is...

Page 804: ...mum pulse length is a steady high level signal The duty factor is 100 count range 00H to FFH MCNTCnm FULL 1 Formula for the duty cycle PWM duty MCMPki 256 with k 1 to 6 and i 0 1 One count cycle is co...

Page 805: ...g MCNTCnm PCE is set to 1 2 Generation of overflow signal start of PWM pulse 3 Generation of match signal timer counter CNTm matches compare register end of PWM pulse OVF overflow CNTm Match signal PW...

Page 806: ...ter MCNTCnm The counting operation is enabled or disabled by the MCNTCnm PCE bit Figure 21 5 Restart Timing after Count Stop Count Start Count Stop Count Start Sequence Count Start Enable counting ope...

Page 807: ...k cycle defined in MCNTCn0 The same accounts for the output signals of drivers 5 and 6 They are controlled by the timer count clock defined in MCNTCn1 Figure 21 6 Output timing of signals SM11 to SM44...

Page 808: ...808 Chapter 21 Stepper Motor Controller Driver Stepper C D Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 809: ...segments The supported addressing method of the LCD is multiplex addressing 22 1 Overview The LCD Controller Driver generates the signals that are necessary for driving an LCD panel Features summary...

Page 810: ...s determined by the frame frequency It can be adjusted via the clock control register LCDC The external signals are listed in the following table Segment Driver Timing Controller Common Driver SEG0 SE...

Page 811: ...potential difference of signals SEG2n 1 and COM1 exceeds VLCD To display a desired pattern on the LCD panel 1 Check what combination of segment and common signals form the desired display pattern 2 W...

Page 812: ...led by means of the following registers Table 22 3 LCD Controller Driver registers overview Register name Shortcut Address LCD clock control register LCDC0 FFFF FB00H LCD mode control register LCDM0 F...

Page 813: ...is determined in the Clock Generator The root clock for LCDCLK can be selected from the main sub or ring oscillator It can be identical with the clock source or it can be a fraction thereof 7 6 5 4 3...

Page 814: ...2 01B LCD clock SPCLK7 SPCLK0 27 125 KHz LCDC0 LCDC0 3 2 10B LCD clock SPCLK9 SPCLK0 29 31 25 KHz Table 22 5 Example settings for frame frequency and duty cycle LCDC03 LCDC02 LCDC01 LCDC00 LCD clocka...

Page 815: ...ister is cleared by any reset The bits 4 to 7 are ignored They should be set to zero 7 6 5 4 3 2 1 0 LCDON0 0 0 LIPS0 0 0 0 0 R W R W R W R W R W R W R W R W Table 22 6 LCDM0 register contents Bit pos...

Page 816: ...duty means each signal COMn is in selection level for one quarter of a frame Figure 22 3 Common signal wave form 1 4 duty 1 3 bias TF frame cycle time TF 4 x T T corresponds to the duty cycle frequen...

Page 817: ...set to non selection level Figure 22 5 shows the selection and non selection level of segment signals Figure 22 5 Selection level and non selection level of segment signals T duty cycle time The tabl...

Page 818: ...f a single digit is given below Each digit is addressed by two segment signals and four common signals Figure 22 6 4 time division LCD pattern and electrode connections Figure 22 7 on page 820 shows t...

Page 819: ...9 Examples of the LCD drive waveforms between SEG28 and the COM0 and COM1 signals are shown in Figure 22 8 on page 821 for the sake of simplicity waveforms for COM2 and COM3 have been omitted When SEG...

Page 820: ...EG11 SEG12 SEG13 SEG14 0 1 0 1 0 0 1 1 0 0 0 1 SEG15 SEG16 SEG17 SEG18 1 0 0 0 1 1 1 0 0 0 0 LCD panel 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 0 Timing strobes SEG20 SEG19 SEG21 1 1 0 1 1 0 1 0 0 SEG22 SE...

Page 821: ...division LCD drive waveforms examples TF VLC0 VLC2 COM0 VLCD 0 COM0 SEG28 VLCD VLC1 1 3VLCD 1 3VLCD VSS1 VLC0 VLC2 COM1 VLC1 VSS1 VLC0 VLC2 COM2 VLC1 VSS1 VLC0 VLC2 COM3 VLC1 VSS1 VLCD 0 COM1 SEG28 VL...

Page 822: ...822 Chapter 22 LCD Controller Driver LCD C D Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 823: ...specific signals that may be required by the LCD controller like address chip select hold and so on If necessary such signals can be provided by general purpose I Os Features summary The LCD Bus Inte...

Page 824: ...face is equipped with a 32 bit register that allows the CPU or DMA to access the data register with 8 16 or 32 bit data accesses The interface automatically generates 1 2 or 4 consecutive 8 bit access...

Page 825: ...individual bytes within the register is prohibited 2 Before writing to or reading from the LBDATA0 register or reading the LBDATAR0 register always make sure that the busy flag LBCTL0 BYF is zero 1 Wr...

Page 826: ...egister have been performed and only the last transferred data shall be read without starting a new LCD bus transfer 23 1 4 Interrupt generation An interrupt is generated on write and read accesses to...

Page 827: ...ce registers overview Register name Shortcut Address LCD Bus Interface control register LBCTL0 FFFF FB60H LCD Bus Interface cycle time register LBCYC0 FFFF FB61H LCD Bus Interface wait states register...

Page 828: ...re WR and RD 1 mod68 mode control signals are E and R W 5 to 4 LBC0 1 0 Selects the internal clock LBC01 LBC00 Selected clock 0 0 SPCLK0 0 1 SPCLK1 1 0 SPCLK2 1 1 SPCLK5 3 TCIS0 Select interrupt gener...

Page 829: ...H Initial Value 02H This register is initialized by any reset Note 1 T is the clock period of the selected SPCLK 2 Always keep LBCYC0 2 7 6 5 4 3 2 1 0 0 0 CYC05 CYC04 CYC03 CYC02 CYC01 CYC0 0 R R R W...

Page 830: ...read written in 8 bit or 1 bit units Address FFFF FB62H Initial Value 00H This register is cleared by any reset Note Always keep LBWST0 WST0 LBCYC0 CYC0 2 7 6 5 4 3 2 1 0 0 0 0 WST04 WST03 WST02 WST01...

Page 831: ...s that are transferred consecutively via the bus interface Word The word is split into 4 bytes that are transferred consecutively via the bus interface When the data is split into bytes and transferre...

Page 832: ...BYF0 is cleared A transfer via the LCD Bus Interface starts as soon as the LBDATA0 register is copied to the write buffer This is indicated by the interrupt INTLCD that becomes active provided that L...

Page 833: ...as transferred during a previous read operation to the LBDATA0 register without initiating a further LCD bus transfer Reading the LBDATAR0 register does not change the status of the LBCTL0 BYF0 and LB...

Page 834: ...In mod80 mode DBWR provides the write strobe WR and DBRD the read strobe RD Note 1 T is the clock period of the selected SPCLK 2 CYC is the chosen number of clock cycles LBCYC0 CYC0 Always keep LBCYC0...

Page 835: ...o the external LCD Controller Driver Figure 23 3 Timing mod80 LBTCTL0 IMD0 0 write word LBWST0 WST0 5 LBCYC0 CYC0 8 LBTCTL0 TCIS0 0 Note The timing diagrams are for functional explanation purposes onl...

Page 836: ...bus interface starts with byte 0 The flag LBCTL0 TPF0 is set to indicate that a transfer is in progress 3 Caused by the interrupt the DMA writes a second halfword to LBDATA0 The CPU can write this ha...

Page 837: ...ss 3 Caused by the interrupt the DMA writes a second byte to LBDATA0 The CPU can write this byte as well after it has checked the busy flag LBCTL0 BYF0 The internal bus transfer again takes some clock...

Page 838: ...om the external LCD controller The busy flag LBCTL0 BYF0 is set immediately The transfer in progress flag LBCTL0 TPF0 is set on the rising edge of the clock The data that is read from LBDATA0 belongs...

Page 839: ...for one clock cycle 3 A new read to LBDATA0 is performed while the previous transfer has not been finished cycle time not elapsed The busy flag LBCTL0 BYF0 is set immediately but the new transfer is...

Page 840: ...ode LBCTL0 IMD0 0 with byte transfers In mode68 mode LBCTL0 IMD0 1 the timing is equivalent when the the RD strobe is considered as the low active E signal LBCTL0 EL0 1 Figure 23 8 Timing mod80 LBTCTL...

Page 841: ...rcuit 24 1 Overview The Sound Generator consists of a programmable square wave tone generator and a programmable pulse width modulator Features summary Special features of the Sound Generator are Prog...

Page 842: ...compares the value of the counter SG0FL with the contents of its volume compare buffer The RS flipflop of the PWM is set by the pulses generated by the counter SG0FL It is reset when the SG0FL counter...

Page 843: ...rnal sound system usually below 64 KHz Its match value defines also the 100 volume level The second counter SG0FH generates the tone frequency 245 Hz to 6 KHz Note If the target values of the counters...

Page 844: ...by means of the following registers Table 24 1 Sound Generator registers overview Register name Shortcut Address SG0 frequency low register SG0FL base SG0 frequency high register SG0FH base 2H SG0 vo...

Page 845: ...egister SG0PWM cleared 7 6 5 4 3 2 1 0 0 0 0 PWR 0 0 OS 0a a The 0 value of this bit must not be changed R R R R W R R R W R W Table 24 3 SG0CTL register contents Bit position Bit name Function 4 PWR...

Page 846: ...the maximum sound amplitude 100 PWM duty cycle A 100 duty cycle continually high will be generated if the SG0PWM value is higher than the SG0FL value For details see PWM calculations on page 852 Note...

Page 847: ...input pulse For example If the counter SG0FL generates a frequency of 32 4 KHz a value of 63 would generate a tone frequency of 253 Hz 3 The value read from this register does not necessarily reflect...

Page 848: ...ster SG0FL The register SG0FL specifies the maximum value of the counter SG0FL For the calculation of the resulting duty cycle refer to PWM calculations on page 852 The setting takes effect after the...

Page 849: ...e the sound volume Therefore it is obligatory to write the correct PWM value to SG0PWM before a new SG0F value is copied to the frequency buffers The SG0F register contents is copied to the buffers wh...

Page 850: ...e information is generated by comparing the SG0FL counter value with the contents of the SG0PWM volume buffer An RS flipflop is set when the counter matches the SG0FL buffer and reset when the counter...

Page 851: ...lume compare buffer can be changed by writing to the volume register SG0PWM If the register is cleared by writing 0000H the register value is copied to the volume compare buffer with the next rising e...

Page 852: ...uffer SG0FL buffer Duty cycle 100 If 0 SG0PWM buffer SG0FL buffer Duty cycle SG0PWM buffer SG0FL buffer 1 where SG0PWM buffer contents of SG0PWM buffer SG0FL buffer contents of SG0FL buffer Example If...

Page 853: ...alue to the volume register SG0PWM Before starting the sound all other register settings must be made The sound is stopped by writing 0000H to the volume register SG0PWM The sound is stopped regardles...

Page 854: ...854 Chapter 24 Sound Generator SG Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 855: ...ns Table 25 1 Naming convention of power supply pins Dedicated function VDD or VSS 5 n none CPU core internal memory and peripherals VDD Voltage Drain Drain VSS Voltage for Substrate and Source level...

Page 856: ...nnected to voltage regulator 0 REGC1 Capacitor for voltage regulator 1 for pin pair VDD51 VSS51 VDD52 VSS52 Clock generation circuit and peripherals Power on clear circuit Pin pair is connected to a v...

Page 857: ...nal assignment of power supply pins PD70 F 3420 PD70 F 3421 PD70 F 3422 PD70F3423 ADC VC AVREF AVDD AVSS Standard I O BVDD50 BVSS50 VSS50 n c REGC0 SMVSS51 SMVDD51 SMVSS50 SMVDD50 VDD52 REGC2 VSS52 VS...

Page 858: ...ment of power supply pins PD70F3424 PD70F3425 PD70F3426 ADC VC AVREF AVDD AVSS CPU RAM Flash Standard I O Regulator 0 BVDD50 BVSS50 VSS50 VDD50 REGC0 SMVSS51 SMVDD51 SMVSS50 SMVDD50 VDD52 REGC2 VSS52...

Page 859: ...Standard I O Regulator 0 BVDD50 BVSS50 VSS50 VDD50 REGC0 SMVSS51 SMVDD51 SMVSS50 SMVDD50 VSS51 REGC1 VDD51 BVSS50 BVDD50 Stepper Motor I O ClockGen Peripherals POC VDD52 REGC2 VSS52 Regulator 1 BVDD51...

Page 860: ...e regulators operate per default in all operation modes normal operation HALT IDLE STOP WATCH Sub WATCH and during RESET During power save modes the voltage regulators can be optionally disabled by se...

Page 861: ...POC Overflow of the Watchdog Timer internal signal RESWDT Main or sub oscillator fails internal signals RESCMM RESCMS As output the reset function provides two internal reset signals SYSRES system res...

Page 862: ...reset SYSRESWDT SYSRESWDT is activated by Power On Clear and external RESET only Both resets provoke different reset behaviour of the Watchdog Timer For details refer to the Watchdog Timer WDT on pag...

Page 863: ...ator Operates Starts oscillation The ring oscillator clock is the default clock source after reset release SSCG clock Stops operation Stoppeda PLL clock Stops operation Stoppeda CPU system clock VBCLK...

Page 864: ...egister ECR 0000 0000H 0000 0000H Program status word PSW 0000 0020H 0000 0020H if no security flags or variable reset vector are set 0000 0021H else Status save registers during CALLT execution CTPC...

Page 865: ...eset the RESSTAT register is cleared and the RESSTAT RESPOC bit is set RESSTAT 01H refer also to RESSTAT Reset source flag register on page 868 for the interaction between Power On Clear and external...

Page 866: ...e in the controller the external RESET can keep the controller in reset state Note The internal system reset signals SYSRES and SYSRESWDT keep their active level for at least four system clock cycles...

Page 867: ...Clock Monitors generate a reset when either the main oscillator or the sub oscillator fails After a Clock Monitor reset the corresponding bit RESSTAT RESCMM or RESSTAT RESCMS is set The system reset s...

Page 868: ...ower On Clear reset sets RESSTAT 01H External RESET sets RESSTAT 02H Special caution is required if both reset events are active concurrently If the Power On Clear reset is longer active than the exte...

Page 869: ...set and external RESET has been released simultaneously RESSTAT 03H That means RESSTAT indicate the occurrence of both reset events All other reset events just set their respective bit in RESSTAT and...

Page 870: ...870 Chapter 26 Reset Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 871: ...er consumption By this it can avoid that its own power supply is dropping below the operating conditions Features summary The Voltage Comparator has the following special features Comparison of an ext...

Page 872: ...1 2 Comparison results Voltage comparison leads to the following results Output signal VCMPO0 and flag VCSTRn VCFn VCMPn VLVI The output signal VCMPO0 of the Voltage Comparator is low for n 0 and the...

Page 873: ...e 00H This register is cleared by any reset Table 27 1 Voltage Comparator registers overview Register name Shortcut Address Voltage Comparator n control register VCCTLn base Voltage Comparator n statu...

Page 874: ...edges are specified VCCTLn VCEn 01B or 11B 2 VCSTRn Voltage Comparator n status register The 8 bit VCSTRn register reflects the result of the voltage comparison Access This register is read only in 8...

Page 875: ...pt INTVCn is generated at the falling edge VCCTLn ESTn 1 0 00B of the comparator s output signal Figure 27 2 Voltage Comparator timing Note For details on the delay time refer to the Electrical Target...

Page 876: ...876 Chapter 27 VoltageComparator Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 877: ...reset function The CPU can be started in the debug mode immediately after reset of the CPU is released 5 Forced break function Execution of the user program can be forcibly aborted 6 Hardware break f...

Page 878: ...ending on the debugger to be used certain peripheral macros can be configured to continue or to stop operation upon a breakpoint hit Functions that are always stopped during break Watchdog Timer Funct...

Page 879: ...s or disables use of the N Wire emulator Bit 7 of address 0000 0079H 0 disabled N Wire emulator cannot connect to the on chip debug unit 1 enabled N Wire emulator can connect to the on chip debug unit...

Page 880: ...ecial sequence of instructions Please refer to RSUDISCP RSUDISC write protection register on page 881 for details Address FFFF F9E0H Initial Value 00H This register is cleared by Power On Clear reset...

Page 881: ...ccesses are ignored Thus the value of RSUDISC can only be rewritten in a specified sequence and illegal write access is inhibited Access This register can only be written in 8 bit units Address FFFF F...

Page 882: ...reset source 2 Power On Clear RESPOC RESPOC Power On Clear reset sets OCDM OCDM0 0 i e the pins are defined as port pins The debugger can not communicate with the controller and the N Wire debug circu...

Page 883: ...PDC05 The DRST signal depicts the N Wire interface reset signal If DRST 0 the on chip debug unit is kept in reset state and does not impact normal controller operation DRST is driven by the debugger...

Page 884: ...evel and to take control over the CPU On start of the debugger the entire controller is reset i e all registers are set to their default states and the CPU s program counter is set to the reset vector...

Page 885: ...this OCDM OCDM0 is set to 1 thus the N Wire interface is enabled With this method the user s program does not need to perform OCDM OCDM0 1 Figure 28 3 N Wire activation by RESET pin normal operation...

Page 886: ...Other connectors like for instance MICTOR connector product name 2 767004 2 Tyco Electronics AMP K K are available as well For the mechanical and electrical specification of these connectors refer to...

Page 887: ...or for emulator connection target system side and Table 28 3 on page 888 shows the pin functions Figure 28 5 Pin configuration of connector for emulator connection target system side Caution Evaluate...

Page 888: ...A7 DDI Input Data input for N Wire interface A8 DCK Input Clock input for N Wire interface A9 DMS Input Transfer mode select input for N Wire interface A10 DDO Output Data output for N Wire interface...

Page 889: ...me emulators input an external reset signal as shown in Figure 28 6 to set the OCDM OCDM0 bit to 1 5 The FLMD0 signal is not required but may be connected Caution The N Wire emulator may not support a...

Page 890: ...can set software breakpoints in the internal flash memory the breakpoints temporarily become invalid when pin reset or internal reset is effected The breakpoints become valid again if a break such as...

Page 891: ...Block Transmission register C0GMABT R W 0x006 CAN0 Global Macro Automatic Block Transmission register low byte C0GMABTL R W R W 0x007 CAN0 Global Macro Automatic Block Transmission register high byte...

Page 892: ...AN1 Global Macro Control register high byte C1GMCTRLH R W R W 0x602 CAN1 Global Macro Clock Selection register C1GMCS R W R W 0x606 CAN1 Global Macro Automatic Block Transmission register C1GMABT R W...

Page 893: ...List Get Pointer register C1RGPT R W 0x660 CAN1 Module Receive History List Get Pointer register low byte C1RGPTL R W R W 0x662 CAN1 Module Last Out Pointer register C1LOPT R 0x664 CAN1 Module Transmi...

Page 894: ...H DSAH2 R W 0xFFFFF094 DMA destination address register 2L DDAL2 R W 0xFFFFF096 DMA destination address register 2H DDAH2 R W 0xFFFFF098 DMA source address register 3L DSAL3 R W 0xFFFFF09A DMA source...

Page 895: ...F11E Interrupt control register of INTP1 P1IC R W R W 0xFFFFF120 Interrupt control register of INTP2 P2IC R W R W 0xFFFFF122 Interrupt control register of INTP3 P3IC R W R W 0xFFFFF124 Interrupt contr...

Page 896: ...W 0xFFFFF16C Interrupt control register of INTTG1CC5 TG1CC5IC R W R W 0xFFFFF172 Interrupt control register of INTAD ADIC R W R W 0xFFFFF174 Interrupt control register of INTC0ERR C0ERRIC R W R W 0xFF...

Page 897: ...TG2CC5IC R W R W 0xFFFFF1C2 Interrupt control register of INTCB1RE CB1REIC R W R W 0xFFFFF1C4 Interrupt control register of INTCB1R CB1RIC R W R W 0xFFFFF1C6 Interrupt control register of INTCB1T CB1T...

Page 898: ...2B ADC result register high byte channel 13 ADCR0H13 R R 0xFFFFF22C ADC result register channel 14 ADCR014 R 0xFFFFF22D ADC result register high byte channel 14 ADCR0H14 R R 0xFFFFF22E ADC result regi...

Page 899: ...put characteristic control register P4 PICC4 R W R W 0xFFFFF38A Port input characteristic control register P5 PICC5 R W R W 0xFFFFF38C Port input characteristic control register P6 PICC6 R W R W 0xFFF...

Page 900: ...W 0xFFFFF42A Port mode register port 5 PM5 R W R W 0xFFFFF42C Port mode register port 6 PM6 R W R W 0xFFFFF430 Port mode register port 8 PM8 R W R W 0xFFFFF432 Port mode register port 9 PM9 R W R W 0x...

Page 901: ...WT1CNT0 R 0xFFFFF572 Non synchronized counter read register WT1 WT1CNT1 R 0xFFFFF574 Counter reload register WT1 WT1R R W 0xFFFFF576 Control register WT1 WT1CTL R W R W 0xFFFFF590 Watchdog timer Frequ...

Page 902: ...mer Output Control register TOC00 R W R W 0xFFFFF600 TMZ0 Synchronized counter read register TZ0CNT0 R 0xFFFFF602 TMZ0 non synchronized counter read register TZ0CNT1 R 0xFFFFF604 TMZ0 counter reload r...

Page 903: ...L R W R W 0xFFFFF660 TMP0 timer control register 0 TP0CTL0 R W R W 0xFFFFF661 TMP0 timer control register 1 TP0CTL1 R W R W 0xFFFFF662 TMP0 timer specific I O control register 0 TP0IOC0 R W R W 0xFFFF...

Page 904: ...de register TMG 0 low byte TMGCM0L R W R W 0xFFFFF6A3 Channel mode register TMG 0 high byte TMGCM0H R W R W 0xFFFFF6A4 Output control register TMG 0 OCTLG0 R W 0xFFFFF6A4 Output control register TMG 0...

Page 905: ...ase status TMG 2 TMGST2 R R 0xFFFFF6E8 Timer count register 0 TMG 2 TMG20 R 0xFFFFF6EA Timer count register 1 TMG 2 TMG21 R 0xFFFFF6EC Capture Compare register 0 TMG 2 GCC20 R W 0xFFFFF6EE Capture Com...

Page 906: ...h ROM correction address register 2L CORAD2L R W 0xFFFFF84A VFB flash ROM correction address register 2H CORAD2H R W 0xFFFFF84C VFB flash ROM correction address register 3 CORAD3 R W 0xFFFFF84C VFB fl...

Page 907: ...D5L R W 0xFFFFF8B6 VSB flash correction address register 5H COR2AD5H R W 0xFFFFF8B8 VSB flash correction address register 6 COR2AD6 R W 0xFFFFF8B8 VSB flash correction address register 6L COR2AD6L R W...

Page 908: ...W R W 0xFFFFFB29 LCD RAM data SEGREG009 R W R W 0xFFFFFB29 LCD RAM data SEGREG029 R W R W 0xFFFFFB30 LCD RAM data SEGREG010 R W R W 0xFFFFFB30 LCD RAM data SEGREG030 R W R W 0xFFFFFB31 LCD RAM data S...

Page 909: ...xFFFFFD04 CSIB0 received data register low byte CB0RX0L R 0xFFFFFD04 CSIB0 received data register CB0RX0 R 0xFFFFFD06 CSIB0 send data register CB0TX0 R W 0xFFFFFD06 CSIB0 send data register low byte C...

Page 910: ...on register odd prescaler 0 OCKS0 R W R W 0xFFFFFDB0 Clock selection register odd prescaler 1 OCKS1 R W R W 0xFFFFFDC0 Pre scalar mode register PRSM0 R W R W 0xFFFFFDC1 Pre scalar compare register PRS...

Page 911: ...If a preceded NPB access is still ongoing the CPU stops until this access is finished and the NPB is cleared In the following formulas are given to calculate the access times Ta when the CPU reads fr...

Page 912: ...ula Access W Formula Register all other Access R W no write access during timer operation Formula Ta SUWL VSWL 3 ru fVBCLK 2 VSWL fPCLK0 1 2 VSWL 1 fVBCLK Ta SUWL VSWL 3 ru 5 fVBCLK 2 VSWL fPCLK0 1 2...

Page 913: ...Register TZnCNT1 Access R Formular Register TZnR Access R Formular Access W Formular Register TZnCTL Access R W Formular Ta SUWL 3 VSWL 6 1 fVBCLK 2 fPCLK2 Ta SUWL VSWL 3 1 fVBCLK Ta SUWL VSWL 3 1 fV...

Page 914: ...ration Formular for multiple write within 7 SPCLK0 periods for single write within 7 SPCLK0 periods Register all other Access R W no write access during timer operation Formular Ta SUWL VSWL 3 ru fVBC...

Page 915: ...gister all other Access R W Formular B 5 Watch Calibration Timer Register CR01 Access R W Formular Access Read Modify Write Formular Register all other Access R W Formular Ta SUWL VSWL 3 1 fVBCLK Ta S...

Page 916: ...A Register all Access R W Formular B 8 Clocked Serial Interface CSIB Register all Access R W Formular B 9 I2C Bus Register IICSn Access R Formular Register all other Access R W Formular Ta SUWL VSWL 3...

Page 917: ...R0n Access R Formular Access W Formular Register all other Access R W Formular Ta SUWL VSWL 3 ru 4 fVBCLK 2 VSWL fPCLK0 2 VSWL 1 fVBCLK Ta SUWL VSWL 3 ru 5 fVBCLK 2 VSWL fPCLK0 2 VSWL 1 fVBCLK Ta SUWL...

Page 918: ...lar Register all other Access R W Formular B 13 LCD Controller Driver Register all Access R W Formular B 14 LCD Bus Interface Register all Access R W Formular Ta SUWL VSWL 3 1 fVBCLK Ta SUWL VSWL 3 ru...

Page 919: ...Clock Generator Register CGSTAT Access R Formular Access W Formular Register all other Access R W Formular B 17 All other Registers Register all Access R W Formular Ta SUWL VSWL 3 1 fVBCLK Ta SUWL 3...

Page 920: ...920 Appendix B Registers Access Times Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 921: ...ps 9 240 maximum CSI transfer rate for flash programming corrected to 2 5 MHz 9 241 PG FP4 pin functions of FLMD0 FLMD1 corrected 10 257 NPB access timing section added 10 267 caution added to CSCn se...

Page 922: ...922 Revision History Preliminary User s Manual U17566EE1V2UM00 Downloaded from Elcodis com electronic components distributor...

Page 923: ...r BCTn 271 Bus cycle control register BCC 275 C C0ERRIC 210 C0RECIC 210 C0TRXIC 210 C0WUPIC 210 C1ERRIC 210 C1RECIC 210 C1TRXIC 210 C1WUPIC 210 CALLT base pointer CTBP 113 CAN Controller area network...

Page 924: ...s 132 CnBRP 693 CnBTR 693 CnCTRL 683 CnERC 689 CnGMABT 678 CnGMABTD 680 CnGMCS 677 CnGMCTRL 675 CnIE 690 CnINFO 688 CnINTS 691 CnLEC 687 CnLIPT 695 CnLOPT 697 CnMASKaH 681 CnMASKaL 681 CnMCONFm 705 Cn...

Page 925: ...82 Exception status flag EP 222 Exception trap 222 External bus properties 257 Bus access 258 Bus priority order 257 Bus width 257 External devices Initialization for access 259 Interface timing 284 E...

Page 926: ...LBWST 830 LCD Activation of segments 818 Panel addressing 811 LCD Bus Interface 823 Access modes 825 Interrupt generation 826 Registers 827 Timing 834 LCD Bus Interface control regis ter LBCTL 828 LCD...

Page 927: ...ster PMn 42 Port open drain control register PODCn 49 Port pin read register PPRn 47 Port register Pn 46 Power save control register PSC 159 Power save mode control regis ter PSM 157 Power Save Modes...

Page 928: ...mparator 872 Stand by control protection reg ister STBCTLP 162 Stand by control register STBCTL 161 STBCTL 161 STBCTLP 162 Stepper Motor Controller Driver 795 Operation 803 Registers 797 STOP mode 173...

Page 929: ...register 0 UAnCTL0 511 UARTAn control register 1 UAnCTL1 534 UARTAn control register 2 UAnCTL2 535 UARTAn option control register 0 UAnOPT0 513 UARTAn receive data register UAnRX 517 UARTAn receive sh...

Page 930: ...T0 Watch Timer 0 477 WT1 Watch Timer 1 477 WTn non synchronized counter read register WTnCNT1 483 WTn synchronized counter reg ister WTnCNT0 483 WTn timer control register WTnCTL 482 WTnCNT0 483 WTnCN...

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