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Chapter 13
16-bit Multi-Purpose Timer G (TMG)
Preliminary User’s Manual U17566EE1V2UM00
(b) Timing of capture trigger edge detection
The Tin inputs are fitted with an edge-detection and noise-elimination circuit.
Because of this circuit, 3 periods to less than 4 periods of the count clock are
required from edge input until an interrupt signal is output and capture
operation is performed. The timing chart is shown below.
Basic settings (x = 0, 1 and y = 0 to 5):
Figure 13-4
Timing of capture trigger edge detection (free run)
Bit
Value
Remark
CSEx2
0
Count clock =
f
SPCLK0
/4
CSEx1
1
CSEx0
0
IEGny1
1
detection of both edges
IEGny0
1
t+2
t+3
t+4
t+5
t+6
t+7
t+7
t
t +1
t+4
t+8
TMGn0/TMGn1
TIGn0
INTTGnCCy
GCCny
3 count clock periods
f
COUNTx
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