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Chapter 5
Interrupt Controller (INTC)
Preliminary User’s Manual U17566EE1V2UM00
Figure 5-16
Pipeline operation at interrupt request acknowledgment (outline)
Note
INT1 to INT4: Interrupt acknowledgement processing
IFx:
Invalid instruction fetch
IDx:
Invalid instruction decode
Note
If the same interrupt occures during the interrupt acknowledge time of 5 cycles,
this new interrupt will discarded. The next interrupt of the same source will only
be registered after these 5 cycles.
5.9 Periods in Which Interrupts Are Not Acknowledged
An interrupt is acknowledged while an instruction is being executed. However,
no interrupt will be acknowledged between an interrupt non-sample instruction
and the next instruction.
The interrupt request non-sampling instructions are as follows:
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (for PSW)
• The store instruction for the interrupt control register (PlCn), in-service
priority register (ISPR), and command register (PRCMD).
Table 5-4
Interrupt response time
Interrupt response time (internal system clocks)
Condition
Internal interrupt
External interrupt
Minimum
5
5 + analog delay time
The following cases are exceptions:
• In IDLE/software STOP mode
• External bit access
• Two or more interrupt request non-
sample instructions are executed
• Access to interrupt control register
Maximum
11
11 + analog delay time
IF
ID
EX
VBCLK (Input)
Instruction 1
Instruction 2
Interrupt acknowledgement operation
Instruction (first instruction of
interrupt service routine)
Interrupt request
IF
ID
EX MEM WB
IFX
IDX
INT1 INT2 INT3 INT4
5 system clocks
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