487
Watch Timer (WT)
Chapter 14
Preliminary User’s Manual U17566EE1V2UM00
As a consequence, register WT1CNT does not show the correct number of
INTWT0UV events after WT1R > 0, but a value of four less:
– 1 INTWT0UV cycle 2 –> 3 taken for the cycle WT1R is written
– 3 INTWT0UV cycles 3 –> 4 –> 5 –> 6 for WT1R validation time
The above calculation assumes that WT1R is written within one INTWT0UV
cycle, which is highly probable, considering INTWT0UV to be the "one second
tick".
However, it may happen that the write to WT1R is delayed because of other
circumstances (nested interrupts, DMA transfers, etc.) and may happen after
S/W counter state 3.
Thus, WT1 would start later, since the 3 clock WTR1 validation time is
maintained.
In order to recognize that situation, read the WT1CNT1 register and compare
its contents with the value written to WT1R. If both are equal, WTR1 has been
written before S/W counter state 3, add four when reading WT1CNT. If they are
not equal check again at next INTWT0UV and add the proper number of
correction cycles.
electronic components distributor
