NEC V850E/Dx3, Preliminary User'S Manual

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DMA Controller (DMAC) Chapter 8
Preliminary User’s Manual U17566EE1V2UM00
Note The next condition can be set even during DMA transfer because the DSAn,
DDAn, and DBCn registers are buffered registers. However, the setting to the
DADCn register is invalid (refer to
“Automatic Restart Function” on page 323
and “DADCn - DMA addressing control registers” on page 317 ).
Figure 8-4 shows a forcible termination of a block transfer operation of DMA
channel 1. A transfer containing a new configuration is executed.
Figure 8-4 DMA transfer forcible termination example 2
Note Since the DSALn, DSAHn, DDALn, DDAHn and DBCn registers are buffered
registers, the next transfer condition can be set even during a DMA transfer.
However, a setting in the DADCn register is ignored (refer to
“Automatic
Restart Function” on page 323 )
8.11 DMA Transfer Completion
When DMA transfer ends and the TCn bit of the DCHCn register is set, a DMA
transfer end interrupt (INTDMAn) is issued to the Interrupt Controller (INTC).
DMA Transfer
Request CH1
DSAL1, DSAH1,
DDAL1, DDAH1 DCHC1
(INIT1 bit = 1)
→
→
→
DMA1 CPU CPU CPU CPU DMA1 CPU CPU CPU CPU DMA1 DMA1 DMA1 DMA1 DMA1 DMA1 DMA1
DMA channel 1
terminal count DMA channel 1 transfer is forcibly
terminated and the bus is released
EN1 bit = 1
TC1 bit = 0 EN1 bit 0
TC1 bit 1
Set register
CPU
Set register Set register Set register
EN1 bit 0
TC1 bit = 0
EN1 bit 1
TC1 bit = 0
DSAL1, DSAH1,
DDAL1, DDAH1 DADC1,
DCHC1
→
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