347
16-bit Timer/Event Counter P (TMP)
Chapter 11
Preliminary User’s Manual U17566EE1V2UM00
(1)
TPnCTL0 - TMPn control register 0
The TPnCTL0 register is an 8-bit register that controls the operation of TMPn.
Access
This register can be read/written in 8-bit or 1-bit units.
Address
<base>
Initial Value
00
H
. This register is initialized by any reset.
The same value can always be written to the TPnCTL0 register by software.
Caution
1.
Set the TPnCKS2 to TPnCKS0 bits when the TPnCE bit = 0.
2.
When the value of the TPnCE bit is changed from 0 to 1, the TPnCKS2 to
TPnCKS0 bits can be set simultaneously.
3.
Be sure to clear bits 3 to 6 to 0.
Note
For information about PCLKx, please refer to
“Clock Generator“ on page 129
.
7
6
5
4
3
2
1
0
TPnCE
0
0
0
0
TPnCKS2
TPnCKS1
TPnCKS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 11-3
TPnCTL0 register contents
Bit position
Bit name
Function
7
TPnCE
TMPn operation disable/enable:
0: TMPn operation disabled (TMPn reset asynchroneously: reset of
TPn0PT0.TPnOVF bit, 16-bit counter, timer output (TOPn0, TOPn1 pins)
1: TMPn operation enabled (TMPn operation starts)
2 to 0
TPnCKS[2:0]
Internal count clock selection:
TPnCKS2
TPnCKS1
TPnCKS0 Internal count clock
0
0
0
PCLK0
0
0
1
PCLK01 = PCLK0/2
0
1
0
PCLK02 = PCLK0/4
0
1
1
Prohibited
1
0
0
PCLK4
1
0
1
PCLK5
1
1
0
PCLK6
1
1
1
PCLK7
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