417
16-bit Timer/Event Counter P (TMP)
Chapter 11
Preliminary User’s Manual U17566EE1V2UM00
(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must
be exercised because an overflow may occur more than once from the first
capture trigger to the next. First, an example of incorrect processing is
shown below.
Figure 11-35
Example of incorrect processing when capture trigger interval is long
The following problem may occur when long pulse width is measured in the
free-running timer mode.
<1> Read the TPnCCRm register (setting of the default value of the
TIPnm pin input).
<2> An overflow occurs. Nothing is done by software.
<3> An overflow occurs a second time. Nothing is done by software.
<4> Read the TPnCCRm register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by
( D
m1
-
D
m0
) (incorrect).
Actually, the pulse width must be ( D
m1
-
D
m0
) because an
overflow occurs twice.
FFFFH
16-
b
it co
u
nter
0000H
TPnCE
b
it
TIPnm pin inp
u
t
TPnCCRm regi
s
ter
INTTPnOV
s
ign
a
l
TPnOVF
b
it
D
m0
D
m1
D
m0
D
m1
<1> <2>
<
3
> <4>
1 cycle of 16-
b
it co
u
nter
P
u
l
s
e width
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