NEC V850E/Dx3, Preliminary User'S Manual

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Chapter 8 DMA Controller (DMAC)
Preliminary User’s Manual U17566EE1V2UM00
8.3.3 DBCn - DMA transfer count registers
These 16-bit registers are used to set the transfer counts for DMA channels n.
They store the remaining transfer counts during DMA transfer.
Since these registers are configured as 2-stage FIFO buffer registers, a new
DMA transfer count for DMA transfer can be specified during DMA transfer
(refer to
“Automatic Restart Function” on page 323 ).
During DMA transfer these registers are decremented by 1 for each transfer
that is performed. DMA transfer is terminated when an underflow occurs (from
0 to FFFFH). On terminal count these registers are rewritten with the value that
was set to the DBCn master register before.
These registers can be read/written in 16-bit units.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address
Initial
value
DBC0 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 B2C BC1 BC0 FFFFF0C0H undef.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address
Initial
value
DBC1 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 B2C BC1 BC0 FFFFF0C2H undef.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address
Initial
value
DBC2 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 B2C BC1 BC0 FFFFF0C4H undef.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address
Initial
value
DBC3 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 B2C BC1 BC0 FFFFF0C6H undef.
Bit position Bit name Function
15 to 0 BC15 to
BC0
Sets the transfer count. It stores the remaining transfer count during DMA transfer.
DBCn States
0000H Transfer count 1 or remaining transfer count
0001H Transfer count 2 or remaining transfer count
: :
FFFFH Transfer count 65,536 (2
16
) or remaining transfer count
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