214
Chapter 5
Interrupt Controller (INTC)
Preliminary User’s Manual U17566EE1V2UM00
5.3.5
IMR0 to IMR5 - Interrupt mask registers
These registers set the interrupt mask state for the maskable interrupts.
The xxMK bit of the IMRm (m = 0 to 5) registers is equivalent to the xxMK bit of
the xxIC register.
IMRm registers can be read/written in 16- and 8-bit units.
The address of the lower 8-bit register IMRmL is equal to that of the 16-bit
IMRm register, and the higher 8-bit register IMRmH can be accessed on the
following address (address (IMRm) + 1).
Caution
Mask bits without function, indicated with “1”, must not be altered. Make sure
to set them “1” when writing to the register.
15
14
13
12
11
10
9
8
Address
Initial value
IMR0
TZ2UVMK TZ1UVMK TZ0UVMK
P6MK
P5MK
P4MK
P3MK
P2MK
FFFFF100H
FFFFH
7
6
5
4
3
2
1
0
P1MK
P0MK
1
TM00MK
WT1UVMK WT0UVMK
VC1MK
VC0MK
15
14
13
12
11
10
9
8
Address
Initial value
IMR1
TG0OV0MK TP3CC1MK TP3CC0MK TP3OVMK TP2CC1MK TP2CC0MK TP2OVMK TP1CC1MK FFFFF102H
FFFFH
7
6
5
4
3
2
1
0
TP1CC0MK TP1OVMK TP0CC1MK TP0CC0MK TP0OVMK TZ5UVMK TZ4UVMK TZ3UVMK
15
14
13
12
11
10
9
8
Address
Initial value
IMR2
TY0UV0MK TG1CC5MK TG1CC4MK TG1CC3MK TG1CC2MK TG1CC1MK TG1CC0MK TG1OV1MK FFFFF104H
FFFFH
7
6
5
4
3
2
1
0
TG1OV0MK TG0CC5MK TG0CC4MK TG0CC3MK TG0CC2MK TG0CC1MK TG0CC0MK TG0OV1MK
15
14
13
12
11
10
9
8
Address
Initial value
IMR3
IIC0MK
UA1TMK
UA1RMK
UA1REMK
UA0TMK
UA0RMK
UA0REMK
CB0TMK
FFFFF106H
FFFFH
7
6
5
4
3
2
1
0
CB0RMK
CB0REMK C0TRXMK C0RECMK C0WUPMK C0ERRMK
ADMK
TY0UV1MK
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