631
I
2
C Bus (IIC)
Chapter 18
Preliminary User’s Manual U17566EE1V2UM00
18.16 Timing of Data Communication
When using I
2
C bus mode, the master device outputs an address via the serial
bus to select one of several slave devices as its communication partner.
After outputting the slave address, the master device transmits the
IICSn.TRCn bit, which specifies the data transfer direction, and then starts
serial communication with the slave device.
The shift operation of the IICn register is synchronized with the falling edge of
the serial clock pin (SCLn). The transmit data is transferred to the SO latch and
is output (MSB first) via the SDAn pin.
Data input via the SDAn pin is captured by the IICn register at the rising edge
of the SCLn pin.
The data communication timing is shown below.
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