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C Bus (IIC)
Chapter 18
Preliminary User’s Manual U17566EE1V2UM00
18.8 Interrupt Request Signal (INTIICn)
The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn
register is generated and the corresponding wait control, as shown below.
Note
1.
The slave device’s INTIICn signal and wait period occur at the falling edge
of the ninth clock only when there is a match with the address set to the
SVAn register.
At this point, the ACK signal is output regardless of the value set to the
IICCn.ACKEn bit. For a slave device that has received an extension code,
the INTIICn signal occurs at the falling edge of the eighth clock.
When the address does not match after restart, the INTIICn signal is
generated at the falling edge of the ninth clock, but no wait occurs.
2.
If the received address does not match the contents of the SVAn register
and an extension code is not received, neither the INTIICn signal nor a wait
occurs.
3.
The numbers in the table indicate the number of the serial clock’s clock
signals. Interrupt requests and wait control are both synchronized with the
falling edge of these clock signals.
(1)
During address transmission/reception
• Slave device operation:
Interrupt and wait timing are determined regardless of the WTIMn bit.
• Master device operation:
Interrupt and wait timing occur at the falling edge of the ninth clock
regardless of the WTIMn bit.
(2)
During data reception
• Master/slave device operation: Interrupt and wait timing is determined
according to the WTIMn bit.
(3)
During data transmission
• Master/slave device operation: Interrupt and wait timing is determined
according to the WTIMn bit.
Table 18-4
INTIICn generation timing and wait control
WTIMn Bit
During Slave Device Operation
During Master Device Operation
Address
Data
Reception
Data
Transmission
Address
Data
Reception
Data
Transmission
0
9
Notes 1, 2
8
Note 2
8
Note 2
9
8
8
1
9
Notes 1, 2
9
Note 2
9
Note 2
9
9
9
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